FW82801EB Intel, FW82801EB Datasheet - Page 509

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
19:16
15:14
11:10
Bit
13
12
9
8
Port Test Control — R/W. When this field is 0s, the port is not operating in a test mode. A non-zero
value indicates that it is operating in test mode and the specific test mode is indicated by the specific
value. The encoding of the test mode bits are (0110b – 1111b are reserved):
Bits
0000b
0001b
0010b
0011b
0100b
0101b
Refer to Universal Serial Bus Revision 2.0 Specification, Chapter 7 for details on each test mode.
Reserved — R/W. Should be written to =00b.
Port Owner — R/W. Default = 1b. This bit unconditionally goes to a 0 when the Configured Flag bit
in the USB2.0_CMD register makes a 0 to 1 transition.
System software uses this field to release ownership of the port to a selected host controller (in the
event that the attached device is not a high-speed device). Software writes a 1 to this bit when the
attached device is not a high-speed device. A 1 in this bit means that a companion host controller
owns and controls the port. See Section 4 of the Enhanced Host Controller Interface Specification
for Universal Serial Bus, Revision 1.0 for operational details.
Port Power (PP) — RO. Read-only with a value of 1. This indicates that the port does have power.
Line Status — RO.These bits reflect the current logical levels of the D+ (bit 11) and D– (bit 10) signal
lines. These bits are used for detection of low-speed USB devices prior to the port reset and enable
sequence. This field is valid only when the port enable bit is 0 and the current connect status bit is
set to a 1.
00 = SE0
10 = J-state
01 = K-state
11 = Undefined
Reserved. This bit will return a 0 when read.
Port Reset — R/W. Default = 0. When software writes a 1 to this bit (from a 0), the bus reset
sequence as defined in the Universal Serial Bus Revision 2.0 Specification is started. Software
writes a 0 to this bit to terminate the bus reset sequence. Software must keep this bit at a 1 long
enough to guarantee the reset sequence completes as specified in the Universal Serial Bus
Revision 2.0 Specification.
1 = Port is in Reset.
0 = Port is not in Reset.
NOTE: When software writes a 0 to this bit, there may be a delay before the bit status changes to a
NOTE: System software should not attempt to reset a port if the HCHalted bit in the USB2.0_STS
0. The bit status will not read as a 0 until after the reset has completed. If the port is in high-
speed mode after reset is complete, the host controller will automatically enable this port
(e.g., set the Port Enable bit to a 1). A host controller must terminate the reset and stabilize
the state of the port within 2 milliseconds of software transitioning this bit from 0 to 1.
For example: if the port detects that the attached device is high-speed during reset, then the
host controller must have the port in the enabled state within 2 ms of software writing this bit
to a 0. The HCHalted bit in the USB2.0_STS register should be a 0 before software
attempts to use this bit. The host controller may hold Port Reset asserted to a 1 when the
HCHalted bit is a 1. This bit is 0 if Port Power is 0
register is a 1. Doing so will result in undefined behavior.
Test Mode
Test mode not enabled (Default)
Test J_STATE
Test K_STATE
Test SE0_NAK
Test Packet
Test FORCE_ENABLE
Description
EHCI Controller Registers (D29:F7)
509