FW82801EB Intel, FW82801EB Datasheet - Page 517

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

14.1.4
14.1.5
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
PCISTS—PCI Status Register
(SMBUS—D31:F3)
Address:
Default Value:
effect.
RID—Revision Identification Register
(SMBUS—D31:F3)
Offset Address:
Default Value:
10:9
Bit
7:0
Bit
2:0
15
14
13
12
11
8
7
6
5
4
3
Revision ID (RID) — RO. Refer to the latest Intel
the Revision Identification register.
Detected Parity Error (DPE) — RO. Hardwired to 0.
Signaled System Error (SSE) — RO. Hardwired to 0.
Received Master Abort (RMA) — RO. Hardwired to 0.
Received Target Abort (RTA) — RO. Hardwired to 0.
Signaled Target Abort (STA) — R/WC.
0 = Intel
1 = The function is targeted with a transaction that the ICH5 terminates with a target abort.
DEVSEL# Timing Status (DEVT) — RO. This 2-bit field defines the timing for DEVSEL# assertion for
positive decode.
01 = Medium timing.
Data Parity Error Detected (DPED) — RO. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
User Definable Features (UDF) — RO. Hardwired to 0.
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Capabilities List (CAP_LIST) — RO. Hardwired to 0 because there are no capability list structures in
this function.
Interrupt Status (INTS) — RO. This bit indicates that an interrupt is pending. It is independent from
the state of the Interrupt Enable bit in the PCI Command register.
Reserved
®
ICH5 did not terminate transaction for this function with a target abort.
06
0280h
08h
See Bit Description
–
07h
Description
Description
®
Attributes:
Size:
Attribute:
Size:
ICH5 / ICH5R Specification Update for the value of
SMBus Controller Registers (D31:F3)
RO, R/WC
16 bits
RO
8 bits
517