FW82801EB Intel, FW82801EB Datasheet - Page 520

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

SMBus Controller Registers (D31:F3)
14.1.13
520
HOSTC—Host Configuration Register
(SMBUS—D31:F3)
Address Offset:
Default Value:
7:3
Bit
2
1
0
Reserved
I
0 = SMBus behavior.
1 = The Intel
SMB_SMI_EN — R/W.
0 = SMBus interrupts will not generate an SMI#.
1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer to
SMBus Host Enable (HST_EN) — R/W.
0 = Disable the SMBus Host Controller.
1 = Enable. The SMB Host Controller interface is enabled to execute commands. The INTREN bit
2
C_EN — R/W.
some commands.
Section 5.21.4
needs to be enabled for the SMB Host Controller to interrupt or SMI#. Note that the SMB Host
Controller will not respond to any new requests until all interrupt requests have been cleared.
40h
00h
®
ICH5 is enabled to communicate with I
(Interrupts / SMI#). This bit needs to be set for SMBALERT# to be enabled.
Description
Intel
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
2
C devices. This will change the formatting of
R/W
8 bits