FW82801EB Intel, FW82801EB Datasheet - Page 522

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

SMBus Controller Registers (D31:F3)
14.2.1
522
HST_STS—Host Status Register
(SMBUS—D31:F3)
Register Offset:
Default Value:
All status bits are set by hardware and cleared by the software writing a one to the particular bit
position.
Bit
7
6
5
4
3
Byte Done Status (DS) — R/WC.
0 = Software can clear this by writing a 1 to it.
1 = Host controller received a byte (for Block Read commands) or if it has completed transmission
This bit has no meaning for block transfers when the 32-byte buffer is enabled.
NOTE: When the last byte of a block message is received, the host controller will set this bit.
INUSE_STS — R/WC (special). This bit is used as semaphore among various independent software
threads that may need to use the ICH5’s SMBus logic, and has no other effect on hardware.
0 = After a full PCI reset, a read to this bit returns a 0.
1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will reset the next
SMBALERT_STS — R/WC.
0 = Interrupt or SMI# was not generated by SMBALERT#. Software clears this bit by writing a 1 to it.
1 = The source of the interrupt or SMI# was the SMBALERT# signal. This bit is only cleared by
If the signal is programmed as a GPIO, then this bit will never be set.
FAILED — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The source of the interrupt or SMI# was a failed bus transaction. This bit is set in response to
BUS_ERR — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The source of the interrupt of SMI# was a transaction collision.
of a byte (for Block Write commands) when the 32-byte buffer is not being used. Note that this
bit will be set, even on the last byte of the transfer. This bit is not set when transmission is due to
the D110 interface heartbeat.
read value to 0. Writing a 0 to this bit has no effect. Software can poll this bit until it reads a 0,
and will then own the usage of the host controller.
software writing a 1 to the bit position or by RSMRST# going low.
the KILL bit being set to terminate the host transaction.
However, it will not immediately set the INTR bit (bit 1 in this register). When the interrupt
handler clears the BYTE_DONE_STS bit, the message is considered complete, and the
host controller will then set the INTR bit (and generate another interrupt). Thus, for a block
message of n bytes, the Intel
needs to be implemented to handle these cases.
00h
00h
®
ICH5 will generate n+1 interrupts. The interrupt handler
Intel
Description
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/WC, R/WC (special), RO
8-bits