FW82801EB Intel, FW82801EB Datasheet - Page 527

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

14.2.9
14.2.10
.
14.2.11
.
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RCV_SLVA—Receive Slave Address Register
(SMBUS—D31:F3)
Register Offset:
Default Value:
Lockable:
SLV_DATA—Receive Slave Data Register
(SMBUS—D31:F3)
Register Offset:
Default Value:
Lockable:
This register contains the 16-bit data value written by the external SMBus master. The processor
can then read the value from this register. This register is reset by RSMRST#, but not PCIRST#
AUX_STS—Auxiliary Status Register
(SMBUS—D31:F3)
Register Offset:
Default Value:
Lockable:
15:8
Bit
6:0
Bit
7:0
Bit
7:2
7
1
0
Reserved
SLAVE_ADDR — R/W. This field is the slave address that the Intel
write cycles. the default is not 0, so the SMBus Slave Interface can respond even before the
processor comes up (or if the processor is dead). This register is cleared by RSMRST#, but not by
PCIRST#.
Data Message Byte 1 (DATA_MSG1) — RO. See
Reserved
SMBus TCO Mode (STCO) — RO. This bit reflects the strap setting of TCO compatible mode vs.
Advanced TCO mode.
0 = Intel
1 = ICH5 is in the advanced TCO mode.
CRC Error (CRCE) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set if a received message contained a CRC error. When this bit is set, the DERR bit of
Data Message Byte 0 (DATA_MSG0) — RO. See
the host status register will also be set. This bit will be set by the controller if a software abort
occurs in the middle of the CRC portion of the cycle or an abort happens after the ICH5 has
received the final data bit transmitted by an external slave.
®
ICH5 is in the compatible TCO mode.
09h
44h
No
0Ah
0000h
No
0Ch
00h
No
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Section 5.21.7
SMBus Controller Registers (D31:F3)
Section 5.21.7
for a discussion of this field.
for a discussion of this field.
®
ICH5 decodes for read and
R/W
8 bits
Resume
RO
16 bits
Resume
RW/C, RO
8 bits
Resume
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