FW82801EB Intel, FW82801EB Datasheet - Page 536

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

AC ’97 Audio Controller Registers (D31:F5)
15.1.4
536
PCISTS—PCI Status Register
(Audio—D31:F5)
Offset:
Default Value
Lockable:
PCISTA is a 16-bit status register. Refer to the PCI Local Bus Specification, Revision 2.3 for
complete details on each bit.
10:9
Bit
2:0
15
14
13
12
11
8
7
6
5
4
3
Detected Parity Error (DPE). Not implemented. Hardwired to 0.
Master Abort Status (MAS) — R/WC. Software clears this bit by writing a 1 to it.
0 = No master abort generated.
1 = Bus Master AC '97 2.3 interface function, as a master, generates a master abort.
Reserved — RO. Will always read as 0.
Signaled Target Abort (STA) — RO. Not implemented. Hardwired to 0.
DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field reflects the Intel
timing when performing a positive decode.
01b = Medium timing.
Data Parity Error Detected (DPED) — RO. Not implemented. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. This bit indicates that the ICH5 as a
target is capable of fast back-to-back transactions.
UDF Supported — RO. Not implemented. Hardwired to 0.
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Capabilities List (CAP_LIST) — RO. Indicates that the controller contains a capabilities pointer list.
The first item is pointed to by looking at configuration offset 34h.
Interrupt Status (IS) — RO.
0 = This bit is 0 after the interrupt is cleared.
1 = This bit is 1 when the INTx# is asserted.
Reserved.
Signaled System Error (SSE) — RO. Not implemented. Hardwired to 0.
06
0280h
No
–
07h
Description
Intel
Attribute:
Size:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RO, R/WC
16 bits
Core
®
ICH5's DEVSEL#