FW82801EB Intel, FW82801EB Datasheet - Page 538

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FW82801EB

Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801EB

Lead Free Status / RoHS Status
Not Compliant

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AC ’97 Audio Controller Registers (D31:F5)
15.1.9
15.1.10
538
Note: The tertiary codec cannot be addressed via this address space. The tertiary space is only available
HEADTYP—Header Type Register
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
NAMBAR—Native Audio Mixer Base Address Register
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
The Native PCI Mode Audio function uses PCI Base Address register #1 to request a contiguous
block of I/O space that is to be used for the Native Audio Mixer software interface. The mixer
requires 256 bytes of I/O space. Native Audio Mixer and Modem codec I/O registers are located
from 00h to 7Fh and reside in the codec. Access to these registers will be decoded by the AC ’97
controller and forwarded over the AC-link to the codec. The codec will then respond with the
register value.
In the case of the split codec implementation, accesses to the different codecs are differentiated by
the controller by using address offsets 00h
for the secondary codec.
from the new MMBAR register. This register powers up as read only and only becomes write-able
when the IOSE bit in offset 41h is set.
For description of these I/O registers, refer to the AC ’97 v2.3 Specification.
31:16
15:8
Bit
7:0
Bit
7:1
0
Header Type — RO. Hardwired to 00h.
Hardwired to 0s.
Base Address — R/W. These bits are used in the I/O space decode of the Native Audio Mixer
interface registers. The number of upper bits that a device actually implements depends on how
much of the address space the device will respond to. For the AC ‘97 mixer, the upper 16 bits are
hardwired to 0, while bits 15:8 are programmable. This configuration yields a maximum I/O block
size of 256 bytes for this base address.
Reserved. Read as 0s.
Resource Type Indicator (RTE) — RO. This bit defaults to 0 and changes to 1 if the IOSE bit is set
(D31:F5:Offset 41h, bit 0). When 1, this bit indicates a request for I/O space.
0Eh
00h
No
10
00000001h
No
13h
7Fh for the primary codec and address offsets 80h
Description
Description
Intel
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RO
8 bits
Core
R/W, RO
32 bits
Core
FEh

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