FW82801EB Intel, FW82801EB Datasheet - Page 540

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

AC ’97 Audio Controller Registers (D31:F5)
15.1.13
15.1.14
540
MBBAR—Bus Master Base Address Register
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
This BAR creates 256-bytes of memory space to signify the base address of the bus master
memory space. The lower 64-bytes of the space pointed to by this register point to the same
registers as the MBBAR.
SVID—Subsystem Vendor Identification Register
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
The SVID register, in combination with the Subsystem ID register, enable the operating
environment to distinguish one audio subsystem from the other(s).
This register is implemented as write-once register. Once a value is written to it, the value can be
read back. Any subsequent writes will have no effect.
This register is not affected by the D3
31:8
15:0
Bit
7:3
2:1
Bit
0
Base Address — R/W. This field provides the I/O offset to use for decoding the PCM In, PCM Out,
and Microphone 1 DMA engines.
Reserved. Read as 0s.
Type — RO. Hardwired to 00b to indicate the base address exists in 32-bit address space
Resource Type Indicator (RTE) — RO. Hardwired to 0 to indicate a request for memory space.
Subsystem Vendor ID — R/WO.
1C
00000000h
No
2C
0000h
No
–
–
1Fh
2Dh
HOT
to D0 transition.
Description
Description
Intel
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W, RO
32 bits
Core
R/WO
16 bits
Core