FW82801EB Intel, FW82801EB Datasheet - Page 568

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

AC ’97 Modem Controller Registers (D31:F6)
16.2
568
Table 172. Intel
AC ’97 Modem I/O Space (D31:F6)
In the case of the split codec implementation accesses to the modem mixer registers in different
codecs are differentiated by the controller by using address offsets 00h
and address offsets 80h
the modem mixer registers.
NOTES:
The Global Control (GLOB_CNT) and Global Status (GLOB_STA) registers are aliased to the
same global registers in the audio and modem I/O space. Therefore a read/write to these registers in
either audio or modem I/O space affects the same physical register. Software could access these
registers as bytes, word, DWord quantities, but reads must not cross DWord boundaries.
1. Registers in italics are for functions not supported by the ICH5
2. Software should not try to access reserved registers.
3. The ICH5 supports a modem codec connected to AC_SDIN[2:0], as long as the Codec ID is 00 or 01.
00h:38h
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
50h
52h
54h
56h
58h
5Ah
7Ch
7Eh
Primary
However, the ICH5 does not support more than one modem codec. For a complete list of topologies, see
your ICH5 enabled Platform Design Guide.
®
ICH5 Modem Mixer Register Configuration
Register
80h:B8h
BCh
BEh
C0h
C2h
C4h
C6h
C8h
CAh
CCh
CEh
D0h
D2h
D4h
D6h
D8h
DAh
FCh
FEh
Secondary
–
FEh for the secondary codec.
Intel RESERVED
Extended Modem ID
Extended Modem Stat/Ctrl
Line 1 DAC/ADC Rate
Line 2 DAC/ADC Rate
Handset DAC/ADC Rate
Line 1 DAC/ADC Level Mute
Line 2 DAC/ADC Level Mute
Handset DAC/ADC Level Mute
GPIO Pin Config
GPIO Polarity/Type
GPIO Pin Sticky
GPIO Pin Wake Up
GPIO Pin Status
Misc. Modem AFE Stat/Ctrl
AC ’97 Reserved
Vendor Reserved
Vendor ID1
Vendor ID2
MMBAR Exposed Registers (D31:F6)
Intel
Name
®
Table 172
82801EB ICH5 / 82801ER ICH5R Datasheet
shows the register addresses for
–
7Fh for the primary codec