FW82801EB Intel, FW82801EB Datasheet - Page 570

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

AC ’97 Modem Controller Registers (D31:F6)
16.2.1
16.2.2
570
x_BDBAR—Buffer Descriptor List Base Address Register
(Modem—D31:F6)
I/O Address:
Default Value:
Lockable:
Software can read the register at offset 00h by performing a single, 32-bit read from address offset
00h. Reads across DWord boundaries are not supported.
x_CIV—Current Index Value Register
(Modem—D31:F6)
I/O Address:
Default Value:
Lockable:
Software can read the registers at offsets 04h, 05h and 06h simultaneously by performing a single,
32-bit read from address offset 04h. Software can also read this register individually by doing a
single, 8-bit read to offset 04h. Reads across DWord boundaries are not supported.
31:3
Bit
2:0
Bit
7:5
4:0
Buffer Descriptor List Base Address [31:3] — R/W. These bits represent address bits 31:3. The
entries should be aligned on 8-byte boundaries.
Hardwired to 0.
Hardwired to 0.
Current Index Value [4:0] — RO. These bits represent which buffer descriptor within the list of 16
descriptors is being processed currently. As each descriptor is processed, this value is
incremented.
MBAR + 00h (MIBDBAR),
MBAR + 10h (MOBDBAR)
00000000h
No
MBAR + 04h (MICIV),
MBAR + 14h (MOCIV),
00h
No
Intel
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
32bits
Core
RO
8bits
Core