FW82801EB Intel, FW82801EB Datasheet - Page 581

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

17.1
17.2
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
GCAP_ID—General Capabilities and Identification
Register
Address Offset:
Default Value:
GEN_CONF—General Configuration Register
Address Offset:
Default Value:
63:2
63:32
31:16
Bit
12:8
1
0
Bit
7:0
15
14
13
Reserved. These bits return 0 when read.
Legacy Rout (LEG_RT_CNF) — R/W. If the ENABLE_CNF bit and the LEG_RT_CNF bit are both
set, then the interrupts will be routed as follows:
Overall Enable (ENABLE_CNF) — R/W. This bit must be set to enable any of the timers to
generate interrupts. If this bit is 0, then the main counter will halt (will not increment) and no
interrupts will be caused by any of these timers. For level-triggered interrupts, if an interrupt is
pending when the ENABLE_CNF bit is changed from 1 to 0, the interrupt status indications (in the
various Txx_INT_STS bits) will not be cleared. Software must write to the Txx_INT_STS bits to clear
the interrupts.
NOTE: This bit will default to 0. BIOS can set it to 1 or 0.
• Timer 0 is routed to IRQ0 in 8259 or IRQ2 in the I/O APIC.
• Timer 1 is routed to IRQ8 in 8259 or IRQ8 in the I/O APIC.
• Timer 2-n is routed as per the routing in the timer n config registers.
• If the Legacy Rout bit is set, the individual routing bits for Timers 0 and 1 (APIC) will have no
• If the Legacy Rout bit is not set, the individual routing bits for each of the timers are used.
• This bit will default to 0. BIOS can set it to 1 to enable the legacy routing, or 0 to disable the
Main Counter Tick Period (COUNTER_CLK_PER_CAP) — RO. This field indicates the period at
which the counter increments in femptoseconds (10^-15 seconds). This will return 0429B17F
when read. This indicates a period of 69841279 fs (69.841279 ns).
Vendor ID Capability (VENDOR_ID_CAP) — RO. This is a 16-bit value assigned to Intel.
supported.
Reserved. This bit returns 0 when read.
Counter Size Capability (COUNT_SIZE_CAP) — RO. Hardwired to 1. Counter is 64-bit wide.
Number of Timer Capability (NUM_TIM_CAP) — RO. This field indicates the number of timers in
this block.
02h = Three timers.
Revision Identification (REV_ID) — RO. This indicates which revision of the function is
implemented. Default value will be 01h.
Legacy Rout Capable (LEG_RT_CAP) — RO. Hardwired to 1. Legacy Interrupt Rout option is
impact.
legacy routing.
00h
0429B17F8086A201h
010h
0000h
Description
Description
Attribute:
Size:
Attribute:
Size:
High-Precision Event Timer Registers
RO
64 bits
R/W
64 bits
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