FW82801EB Intel, FW82801EB Datasheet - Page 583

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

17.5
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: The letter n can be 0, 1, or 2, referring to Timer 0, 1 or 2.
TIMn_CONF—Timer n Configuration and
Capabilities Register
Address Offset:
Default Value:
55:52, 43
51:44,
64:56
42:14
13:9
Bit
8
7
6
5
4
Reserved. These bits will return 0 when read.
Timer Interrupt Rout Capability (TIMERn_INT_ROUT_CAP) —RO.
Timer 0, 1:Bits 52, 53, 54, and 55 in this field (corresponding to IRQ 20, 21, 22, and 23) have a
Timer 2:Bits 43, 52, 53, 54, and 55 in this field (corresponding to IRQ 11, 20, 21, 22, and 23) have
NOTE: If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any
Reserved . These bits return 0 when read.
Interrupt Rout (TIMERn_INT_ROUT_CNF) — R/W. This 5-bit field indicates the routing for the
interrupt to the I/O (x) APIC. Software writes to this field to select which interrupt in the I/O (x) will
be used for this timer’s interrupt. If the value is not supported by this particular timer, then the
value read back will not match what is written. The software must only write valid values.
NOTES:
Timer n 32-bit Mode (TIMERn_32MODE_CNF) — R/W or RO. Software can set this bit to force
a 64-bit timer to behave as a 32-bit timer.
Timer 0:Bit is read/write (default to 0). 1 = 64 bit; 0 = 32 bit
Timers 1, 2:Hardwired to 0. Writes have no effect (since these two timers are 32-bits).
Reserved . This bit returns 0 when read.
Timer n Value Set (TIMERn_VAL_SET_CNF) — R/W. Software uses this bit only for Timer 0 if it
has been set to periodic mode. By writing this bit to a 1, the software is then allowed to directly set
the timer’s accumulator. Software does not have to write this bit back to 1 (it automatically clears).
Software should not write a 1 to this bit position if the timer is set to non-periodic mode.
NOTE: This bit will return 0 when read. Writes will only have an effect for Timer 0 if it is set to
Timer n Size (TIMERn_SIZE_CAP) — RO. This read only field indicates the size of the timer.
Timer 0:Value is 1 (64-bits).
Timers 1, 2:Value is 0 (32-bits).
Periodic Interrupt Capable (TIMERn_PER_INT_CAP) — RO. If this bit is 1, the hardware
supports a periodic mode for this timer’s interrupt.
Timer 0: Hardwired to 1 (supports the periodic interrupt).
Timers 1, 2: Hardwired to 0 (does not support periodic interrupt).
1. If the Legacy Rout bit is set, then Timers 0 and 1 will have a different routing, and this bit field
2. Timer 0,1: Software is responsible to make sure it programs a valid value (20, 21, 22, or 23)
3. Timer 2: Software is responsible to make sure it programs a valid value (11, 20, 21, 22, or 23)
has no effect for those two timers.
for this field. The Intel
for this field. The ICH5 logic does not check the validity of the value written.
other devices to guarantee the proper operation of HPET #2.
periodic mode. Writes will have no effect for Timers 1 and 2.
Timer 0: 100–107h,
Timer 1: 120–127h,
Timer 2: 140–147h
N/A
value of 1. Writes will have no effect.
a value of 1. Writes will have no effect.
®
ICH5 logic does not check the validity of the value written.
Description
Attribute:
Size:
High-Precision Event Timer Registers
RO, R/W
64 bits
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