FW82801EB Intel, FW82801EB Datasheet - Page 584

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

High-Precision Event Timer Registers
584
NOTE: Reads or writes to unimplemented timers should not be attempted. Read from any unimplemented
Bit
3
2
1
0
registers will return an undetermined value.
Timer n Type (TIMERn_TYPE_CNF) — R/W or RO.
Timer 0:Bit is read/write. 0 = Disable timer to generate periodic interrupt; 1 = Enable timer to
Timers 1, 2: Hardwired to 0. Writes have no affect.
Timer n Interrupt Enable (TIMERn_INT_ENB_CNF) — R/W. This bit must be set to enable timer
n to cause an interrupt when it times out.
1 = Enable
0 = Disable (Default). The timer can still count and generate appropriate status bits, but will not
Timer Interrupt Type (TIMERn_INT_TYPE_CNF) — R/W.
0 =The timer interrupt is edge triggered. This means that an edge-type interrupt is generated. If
1 =The timer interrupt is level triggered. This means that a level-triggered interrupt is generated.
Reserved. These bits will return 0 when read.
cause an interrupt.
another interrupt occurs, another edge will be generated.
The interrupt will be held active until it is cleared by writing to the bit in the General Interrupt
Status Register. If another interrupt occurs before the interrupt is cleared, the interrupt will
remain active.
generate a periodic interrupt.
Intel
Description
®
82801EB ICH5 / 82801ER ICH5R Datasheet