FW82801EB Intel, FW82801EB Datasheet - Page 613

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FW82801EB

Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801EB

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Intel
®
Table 187. Ultra ATA Timing (Mode 3, Mode 4, Mode 5) (Sheet 2 of 2)
82801EB ICH5 / 82801ER ICH5R Datasheet
NOTES:
1. The specification symbols in parentheses correspond to the AT Attachment
2. See the AT Attachment
Sym
t96a
t96b
t98a
t98b
(ATA/ATAPI
measuring these timing parameters.
t93
t94
t95
t97
t99
STROBE output released-to-
driving to the first transition of
critical timing (Tzfs)
Unlimited Interlock Time (Tui)
Maximum time allowed for
output drivers to release (from
asserted or negated) (Taz)
Drivers to assert or negate (from
released) (Tzad)
Ready-to-final-STROBE time
(no STROBE edges shall be
sent this long after negation of
DMARDY#) (Trfs)
Maximum time before releasing
IORDY (Tiordyz)
Minimum time before driving
IORDY (see Note 2) (Tziordy)
Time from STROBE edge to
negation of DMARQ or assertion
of STOP (when sender
terminates a burst) (Tss)
Data Output Released-to-
Driving Until the First Transition
of Critical Timing (Tdzfs)
6) specification name.
Parameter (1)
6 with Packet Interface (ATA/ATAPI
20.0
Min
50
0
0
0
0
Mode 3
(ns)
Max
10
60
20
Min
6.7
50
0
0
0
0
Mode 4
(ns)
6) specification for further details on
Max
10
60
20
Min
35
25
50
0
0
0
Mode 5
Electrical Characteristics
(ns)
6 with Packet Interface
Max
10
50
20
Measuring
See Note 2
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Connector
Location
Sender
Sender
Sender
Device
Device
Device
Device
Host
14
13
Figure
613

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