FW82801EB Intel, FW82801EB Datasheet - Page 640

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Register Index
640
Table 204. Intel
Capability ID Register
Next Item Pointer
Power Management
Capabilities
Power Management
Control/Status Register
Data Register
Vendor ID
Device ID
PCI Device Command
Register
PCI Device Status Register
Revision ID
Sub Class Code
Base Class Code
Primary Master Latency
Timer
Header Type
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Secondary Master Latency
Timer
IO Base Register
IO Limit Register
Secondary Status Register
Memory Base
Memory Limit
Prefetchable Memory Base
®
Register Name
ICH5 PCI Configuration Registers (Sheet 2 of 11)
DE – DFh
E0 – E1h
1E – 1Fh
04 – 05h
22 – 23h
00 – 01h
02 – 03h
06 – 07h
20 – 21h
24 – 25h
Offset
DCh
DDh
E3h
0Ah
0Bh
0Dh
0Eh
1Ah
1Bh
1Ch
1Dh
08h
18h
19h
Hub Interface to PCI Bridge D30:F0
Section 7.1.20, “CAP_ID — Capability Identification Register
(LAN Controller—B1:D8:F0)” on page 283
Section 7.1.21, “NXT_PTR — Next Item Pointer Register (LAN
Controller—B1:D8:F0)” on page 284
Section 7.1.22, “PM_CAP — Power Management Capabilities
Register (LAN Controller—B1:D8:F0)” on page 284
Section 7.1.23, “PMCSR — Power Management Control/Status
Register (LAN Controller—B1:D8:F0)” on page 285
Section 7.1.24, “PCIDATA — PCI Power Management Data
Register (LAN Controller—B1:D8:F0)” on page 286
Section 8.1.1, “VID—Vendor Identification Register (HUB-PCI—
D30:F0)” on page 302
Section 8.1.2, “DID—Device Identification Register (HUB-PCI—
D30:F0)” on page 302
Section 8.1.3, “PCICMD—PCI Command Register (HUB-PCI—
D30:F0)” on page 303
Section 8.1.4, “PCISTS—PCI Status Register (HUB-PCI—
D30:F0)” on page 304
Section 8.1.6, “SCC—Sub-Class Code Register (HUB-PCI—
D30:F0)” on page 305
Section 8.1.6, “SCC—Sub-Class Code Register (HUB-PCI—
D30:F0)” on page 305
Section 8.1.7, “BCC—Base-Class Code Register (HUB-PCI—
D30:F0)” on page 305
Section 8.1.8, “PMLT—Primary Master Latency Timer Register
(HUB-PCI—D30:F0)” on page 305
Section 8.1.9, “HEADTYP—Header Type Register (HUB-PCI—
D30:F0)” on page 306
Section 8.1.10, “PBUS_NUM—Primary Bus Number Register
(HUB-PCI—D30:F0)” on page 306
Section 8.1.11, “SBUS_NUM—Secondary Bus Number Register
(HUB-PCI—D30:F0)” on page 306
Section 8.1.12, “SUB_BUS_NUM—Subordinate Bus Number
Register (HUB-PCI—D30:F0)” on page 306
Section 8.1.13, “SMLT—Secondary Master Latency Timer
Register (HUB-PCI—D30:F0)” on page 307
Section 8.1.14, “IOBASE—I/O Base Register (HUB-PCI—
D30:F0)” on page 307
Section 8.1.15, “IOLIM—I/O Limit Register (HUB-PCI—D30:F0)”
on page 307
Section 8.1.16, “SECSTS—Secondary Status Register (HUB-
PCI—D30:F0)” on page 308
Section 8.1.17, “MEMBASE—Memory Base Register (HUB-
PCI—D30:F0)” on page 309
Section 8.1.18, “MEMLIM—Memory Limit Register (HUB-PCI—
D30:F0)” on page 309
Section 8.1.19, “PREF_MEM_BASE—Prefetchable Memory
Base Register (HUB-PCI—D30:F0)” on page 309
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Datasheet Section and Location