FW82801EB Intel, FW82801EB Datasheet - Page 643

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 204. Intel
82801EB ICH5 / 82801ER ICH5R Datasheet
Flash BIOS Decode Enable
1 Register
LPC Generic Decode
Range 1
LPC Enables
Flash BIOS Select 1
Register
LPC Generic Decode
Range 2
Flash BIOS Select 2
Register
Flash BIOS Decode Enable
2 Register
Function Disable Register
Vendor ID
Device ID
Command Register
Device Status
Revision ID
Programming Interface
Sub Class Code
Base Class Code
Master Latency Timer
Header Type
Primary Command Block
Base Address
Primary Control Block Base
Address
Secondary Command
Block Base Address
Secondary Control Block
Base Address
Bus Master Base Address
Register
Subsystem Vendor ID
®
Register Name
ICH5 PCI Configuration Registers (Sheet 5 of 11)
ECh – EDh
E8h – EBh
E4h – E5h
E6h – E7h
00h – 01h
02h – 03h
04h – 05h
06h – 07h
20h – 23h
EE – EFh
2C – 2Dh
1C – 1Fh
18 – 1Bh
10 – 13h
14 – 17h
Offset
E3h
0Ah
0Bh
0Dh
0Eh
F0h
F2h
08h
09h
IDE Controller (D31:F1)
Section 9.1.28, “FB_DEC_EN1—Flash BIOS Decode Enable 1
Register (LPC I/F—D31:F0)” on page 336
Section 9.1.29, “GEN1_DEC—LPC I/F Generic Decode Range
1 Register (LPC I/F—D31:F0)” on page 337
Section 9.1.30, “LPC_EN—LPC I/F Enables Register (LPC I/F—
D31:F0)” on page 337
Section 9.1.31, “FB_SEL1—Flash BIOS Select 1 Register (LPC
I/F—D31:F0)” on page 339
Section 9.1.32, “GEN2_DEC—LPC I/F Generic Decode Range
2 Register (LPC I/F—D31:F0)” on page 340
Section 9.1.33, “FB_SEL2—Flash BIOS Select 2 Register (LPC
I/F—D31:F0)” on page 340
Section 9.1.34, “FB_DEC_EN2—Flash BIOS Decode Enable 2
Register (LPC I/F—D31:F0)” on page 341
Section 9.1.35, “FUNC_DIS—Function Disable Register (LPC I/
F—D31:F0)” on page 342
Section 10.1.1, “VID—Vendor Identification Register (IDE—
D31:F0)” on page 416
Section 10.1.2, “DID—Device Identification Register (IDE—
D31:F0)” on page 416
Section 10.1.3, “PCICMD—PCI Command Register (IDE—
D31:F1)” on page 417
Section 10.1.4, “PCISTS — PCI Status Register (IDE—D31:F1)”
on page 418
Section 10.1.5, “RID—Revision Identification Register (IDE—
D31:F1)” on page 419
Section 10.1.7, “SCC—Sub Class Code Register (IDE—
D31:F1)” on page 419
Section 10.1.8, “BCC—Base Class Code Register (IDE—
D31:F1)” on page 420
Section 10.1.9, “PMLT—Primary Master Latency Timer Register
(IDE—D31:F1)” on page 420
Section 10.1.10, “PCMD_BAR—Primary Command Block Base
Address Register (IDE—D31:F1)” on page 420
Section 10.1.11, “PCNL_BAR—Primary Control Block Base
Address Register (IDE—D31:F1)” on page 421
Section 10.1.12, “SCMD_BAR—Secondary Command Block
Base Address Register (IDE D31:F1)” on page 421
Section 10.1.13, “SCNL_BAR—Secondary Control Block Base
Address Register (IDE D31:F1)” on page 421
Section 10.1.14, “BM_BASE — Bus Master Base Address
Register (IDE—D31:F1)” on page 422
Section 10.1.15, “IDE_SVID — Subsystem Vendor Identification
(IDE—D31:F1)” on page 422
Datasheet Section and Location
Register Index
643