FW82801EB Intel, FW82801EB Datasheet - Page 644

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Register Index
644
Table 204. Intel
Subsystem ID
Interrupt Line
Interrupt Pin
Primary/Secondary IDE
Timing
Slave IDE Timing
Synchronous DMA Control
Register
Synchronous DMA Timing
Register
IDE I/O Configuration
Register
Vendor ID
Device ID
Command Register
Device Status
Revision ID
Programming Interface
Sub Class Code
Base Class Code
Master Latency Timer
Header Type
Primary Command Block
Base Address
Primary Control Block Base
Address
Secondary Command
Block Base Address
Secondary Control Block
Base Address
Bus Master Base Address
Register
Subsystem Vendor ID
®
Register Name
ICH5 PCI Configuration Registers (Sheet 6 of 11)
4Ah – 4Bh
40h – 43h
00h – 01h
04h – 05h
06h – 07h
20h – 23h
02h – 03h
2C – 2Dh
2E – 2Fh
1C – 1Fh
10 – 13h
14 – 17h
18 – 1Bh
Offset
3Ch
3Dh
0Ah
0Bh
0Dh
0Eh
44h
48h
54h
08h
09h
SATA Controller (D31:F2)
Section 10.1.16, “IDE_SID — Subsystem Identification Register
(IDE—D31:F1)” on page 422
Section 10.1.17, “INTR_LN—Interrupt Line Register (IDE—
D31:F1)” on page 423
Section 10.1.18, “INTR_PN—Interrupt Pin Register (IDE—
D31:F1)” on page 423
Section 10.1.19, “IDE_TIM — IDE Timing Register (IDE—
D31:F1)” on page 424
Section 10.1.20, “SLV_IDETIM—Slave (Drive 1) IDE Timing
Register (IDE—D31:F1)” on page 425
Section 10.1.21, “SDMA_CNT—Synchronous DMA Control
Register (IDE—D31:F1)” on page 427
Section 10.1.22, “SDMA_TIM—Synchronous DMA Timing
Register (IDE—D31:F1)” on page 428
Section 10.1.23, “IDE_CONFIG—IDE I/O Configuration Register
(IDE—D31:F1)” on page 429
Section 11.1.1, “VID—Vendor Identification Register (SATA—
D31:F2)” on page 434
Section 11.1.2, “DID—Device Identification Register (SATA—
D31:F2)” on page 434
Section 11.1.3, “PCICMD—PCI Command Register (SATA–
D31:F2)” on page 435
Section 11.1.4, “PCISTS — PCI Status Register (SATA–
D31:F2)” on page 436
Section 11.1.6, “PI—Programming Interface Register (SATA–
D31:F2)” on page 437
Section 11.1.7, “SCC—Sub Class Code Register (SATA–
D31:F2)” on page 437
Section 11.1.8, “BCC—Base Class Code Register (SATA–
D31:F2)” on page 438
Section 11.1.9, “PMLT—Primary Master Latency Timer Register
(SATA–D31:F2)” on page 438
Section 11.1.10, “PCMD_BAR—Primary Command Block Base
Address Register (SATA–D31:F2)” on page 438
Section 11.1.11, “PCNL_BAR—Primary Control Block Base
Address Register (SATA–D31:F2)” on page 439
Section 11.1.12, “SCMD_BAR—Secondary Command Block
Base Address Register (IDE D31:F1)” on page 439
Section 11.1.13, “SCNL_BAR—Secondary Control Block Base
Address Register (IDE D31:F1)” on page 439
Section 11.1.14, “BAR — Legacy Bus Master Base Address
Register (SATA–D31:F2)” on page 440
Section 11.1.15, “SVID—Subsystem Vendor Identification
Register (SATA–D31:F2)” on page 440
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Datasheet Section and Location