FW82801EB Intel, FW82801EB Datasheet - Page 65

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

2.20
Intel
®
Table 22. Power and Ground Signals
82801EB ICH5 / 82801ER ICH5R Datasheet
Power and Ground
VccSus1_5_A
VccSus1_5_B
VccSus1_5_C
VccSATAPLL
VccUSBPLL
V5REF_Sus
VccSus3_3
V_CPU_IO
VccRTC
Vcc3_3
Vcc1_5
V5REF
HIREF
Name
Vss
3.3 V supply for core well I/O buffers (18 pins). This power may be shut off in S3, S4, S5 or
G3 states.
1.5 V supply for core well logic and hub interface logic (25 pins). This power may be shut off
in S3, S4, S5, or G3 states.
Reference for 5 V tolerance on core well inputs (2 pins). This power may be shut off in S3,
S4, S5, or G3 states.
350 mV analog input for hub interface (1 pin).
This power is shut off in S3, S4, S5, and G3 states.
3.3 V supply for resume well I/O buffers (10 pins). This power is not expected to be shut off
unless the system is unplugged.
1.5 V supply for resume well logic (1 pin). This power is not expected to be shut off unless
AC power is not available.
NOTE:
1.5 V supply for resume well logic (3 pins). This power is not expected to be shut off unless
AC power is not available.
NOTE:
1.5 V supply for resume well logic (2 pins). This power is not expected to be shut off unless
AC power is not available.
NOTE:
Reference for 5 V tolerance on resume well inputs (1 pin). This power is not expected to be
shut off unless the system is unplugged.
3.3 V (can drop to 1.0 V min. in G3 state) supply for the RTC well (1 pin). This power is not
expected to be shut off unless the RTC battery is removed or completely drained.
NOTE: Implementations should not attempt to clear CMOS by using a jumper to pull
1.5 V supply for core well logic (1 pin). This signal is used for the USB PLL. This power may
be shut off in S3, S4, S5, or G3 states.
1.5 V supply for core well logic (2 pins). This signal is used for the SATA PLL. This power
may be shut off in S3, S4, S5, or G3 states.
Powered by the same supply as the processor I/O voltage (3 pins). This supply is used to
drive the processor interface signals listed in
Grounds (119 pins).
1. This voltage plane is generated internally
2. Do not connect the three sets of VccSus1_5_x signal groups on the Intel
1. This voltage plane is generated internally
2. Do not connect the three sets of VccSus1_5_x signal groups on the ICH5 together. Each
1. This voltage plane is generated internally
2. Do not connect the three sets of VccSus1_5_x signal groups on the ICH5 together. Each
together. Each group needs to be independently connected to its corresponding
decoupling capacitor for optimum noise isolation.
group needs to be independently connected to its corresponding decoupling capacitor
for optimum noise isolation.
group needs to be independently connected to its corresponding decoupling capacitor
for optimum noise isolation.
VccRTC low. Clearing CMOS in an ICH5-based platform can be done by using a
jumper on RTCRST# or GPI, or using SAFEMODE strap.
Description
Table
14.
Signal Description
®
ICH5
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