FW82801EB Intel, FW82801EB Datasheet - Page 650

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Register Index
650
Table 205. Intel
Channel 0 DMA Base &
Current Address Register
Channel 0 DMA Base &
Current Count Register
Channel 1 DMA Base &
Current Address Register
Channel 1 DMA Base &
Current Count Register
Channel 2 DMA Base &
Current Address Register
Channel 2 DMA Base &
Current Count Register
Channel 3 DMA Base &
Current Address Register
Channel 3 DMA Base &
Current Count Register
Channel 0 – 3 DMA
Command Register
Channel 0 – 3 DMA Status
Register
Channel 0 – 3 DMA Write
Single Mask Register
Channel 0 – 3 DMA Channel
Mode Register
Channel 0 – 3 DMA Clear
Byte Pointer Register
Channel 0 – 3 DMA Master
Clear Register
Channel 0 – 3 DMA Clear
Mask Register
Channel 0 – 3 DMA Write All
Mask Register
Aliased at 00h – 0Fh
Master PIC ICW1 Init. Cmd
Word 1 Register
Master PIC OCW2 Op Ctrl
Word 2 Register
Master PIC OCW3 Op Ctrl
Word 3 Register
Master PIC ICW2 Init. Cmd
Word 2 Register
Master PIC ICW3 Init. Cmd
Word 3 Register
Master PIC ICW4 Init. Cmd
Word 4 Register
Master PIC OCW1 Op Ctrl
Word 1 Register
Aliased at 20h – 21h
Aliased at 20h – 21h
®
Register Name
ICH5 Fixed I/O Registers (Sheet 1 of 5)
10h – 1Fh
24h – 25h
28h – 29h
Port
0Ah
0Bh
0Ch
0Dh
0Eh
00h
01h
02h
03h
04h
05h
06h
07h
08h
0Fh
20h
21h
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers (LPC I/F—D31:F0)” on page 345
Section 9.2.2, “DMABASE_CC—DMA Base and Current Count
Registers (LPC I/F—D31:F0)” on page 346
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers (LPC I/F—D31:F0)” on page 345
Section 9.2.2, “DMABASE_CC—DMA Base and Current Count
Registers (LPC I/F—D31:F0)” on page 346
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers (LPC I/F—D31:F0)” on page 345
Section 9.2.2, “DMABASE_CC—DMA Base and Current Count
Registers (LPC I/F—D31:F0)” on page 346
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers (LPC I/F—D31:F0)” on page 345
Section 9.2.2, “DMABASE_CC—DMA Base and Current Count
Registers (LPC I/F—D31:F0)” on page 346
Section 9.2.4, “DMACMD—DMA Command Register (LPC I/F—
D31:F0)” on page 347
Section 9.2.5, “DMASTA—DMA Status Register (LPC I/F—
D31:F0)” on page 347
Section 9.2.6, “DMA_WRSMSK—DMA Write Single Mask
Register (LPC I/F—D31:F0)” on page 348
Section 9.2.7, “DMACH_MODE—DMA Channel Mode Register
(LPC I/F—D31:F0)” on page 349
Section 9.2.8, “DMA Clear Byte Pointer Register (LPC I/F—
D31:F0)” on page 349
Section 9.2.9, “DMA Master Clear Register (LPC I/F—D31:F0)”
on page 350
Section 9.2.10, “DMA_CLMSK—DMA Clear Mask Register
(LPC I/F—D31:F0)” on page 350
Section 9.2.11, “DMA_WRMSK—DMA Write All Mask Register
(LPC I/F—D31:F0)” on page 350
Section 9.4.2, “ICW1—Initialization Command Word 1 Register
(LPC I/F—D31:F0)” on page 356
Section 9.4.8, “OCW2—Operational Control Word 2 Register
(LPC I/F—D31:F0)” on page 359
Section 9.4.9, “OCW3—Operational Control Word 3 Register
(LPC I/F—D31:F0)” on page 360
Section 9.4.3, “ICW2—Initialization Command Word 2 Register
(LPC I/F—D31:F0)” on page 357
Section 9.4.4, “ICW3—Master Controller Initialization Command
Word 3 Register (LPC I/F—D31:F0)” on page 357
Section 9.4.6, “ICW4—Initialization Command Word 4 Register
(LPC I/F—D31:F0)” on page 358
Section 9.4.7, “OCW1—Operational Control Word 1 (Interrupt
Mask) Register (LPC I/F—D31:F0)” on page 359
Intel
®
Datasheet Section and Location
82801EB ICH5 / 82801ER ICH5R Datasheet