FW82801EB Intel, FW82801EB Datasheet - Page 653

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 205. Intel
82801EB ICH5 / 82801ER ICH5R Datasheet
Channel 4 DMA Base &
Current Address Register
Aliased at C0h
Channel 4 DMA Base &
Current Count Register
Aliased at C2h
Channel 5 DMA Base &
Current Address Register
Aliased at C4h
Channel 5 DMA Base &
Current Count Register
Aliased at C6h
Channel 6 DMA Base &
Current Address Register
Aliased at C8h
Channel 6 DMA Base &
Current Count Register
Aliased at CAh
Channel 7 DMA Base &
Current Address Register
Aliased at CCh
Channel 7 DMA Base &
Current Count Register
Aliased at CEh
Channel 4 – 7 DMA
Command Register
Channel 4 – 7 DMA Status
Register
Aliased at D0h
Channel 4 – 7 DMA Write
Single Mask Register
Aliased at D4h
Channel 4 – 7 DMA Channel
Mode Register
Aliased at D6h
Channel 4 – 7 DMA Clear
Byte Pointer Register
Aliased at D8h
Channel 4 – 7 DMA Master
Clear Register
Aliased at DAh
Channel 4 – 7 DMA Clear
Mask Register
Aliased at DCh
Channel 4 – 7 DMA Write All
Mask Register
®
Register Name
ICH5 Fixed I/O Registers (Sheet 4 of 5)
Port
CAh
CBh
CCh
CDh
CEh
DAh
DBh
DCh
DEh
DEh
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CFh
D0h
D1h
D4h
D5h
D6h
D7h
D8h
D9h
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers (LPC I/F—D31:F0)” on page 345
Section 9.2.2, “DMABASE_CC—DMA Base and Current Count
Registers (LPC I/F—D31:F0)” on page 346
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers (LPC I/F—D31:F0)” on page 345
Section 9.2.2, “DMABASE_CC—DMA Base and Current Count
Registers (LPC I/F—D31:F0)” on page 346
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers (LPC I/F—D31:F0)” on page 345
Section 9.2.2, “DMABASE_CC—DMA Base and Current Count
Registers (LPC I/F—D31:F0)” on page 346
Section 9.2.1, “DMABASE_CA—DMA Base and Current
Address Registers (LPC I/F—D31:F0)” on page 345
Section 9.2.2, “DMABASE_CC—DMA Base and Current Count
Registers (LPC I/F—D31:F0)” on page 346
Section 9.2.4, “DMACMD—DMA Command Register (LPC I/F—
D31:F0)” on page 347
Section 9.2.5, “DMASTA—DMA Status Register (LPC I/F—
D31:F0)” on page 347
Section 9.2.6, “DMA_WRSMSK—DMA Write Single Mask
Register (LPC I/F—D31:F0)” on page 348
Section 9.2.7, “DMACH_MODE—DMA Channel Mode Register
(LPC I/F—D31:F0)” on page 349
Section 9.2.8, “DMA Clear Byte Pointer Register (LPC I/F—
D31:F0)” on page 349
Section 9.2.9, “DMA Master Clear Register (LPC I/F—D31:F0)”
on page 350
Section 9.2.10, “DMA_CLMSK—DMA Clear Mask Register
(LPC I/F—D31:F0)” on page 350
Section 9.2.11, “DMA_WRMSK—DMA Write All Mask Register
(LPC I/F—D31:F0)” on page 350
Datasheet Section and Location
Register Index
653