FW82801EB Intel, FW82801EB Datasheet - Page 7

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
5.5
5.6
5.7
5.8
DMA Operation (D31:F0) ..................................................................................................109
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
PCI DMA ...........................................................................................................................113
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
5.6.8
5.6.9
5.6.10 General Flow of DMA Transfers ..........................................................................117
5.6.11 Terminal Count ....................................................................................................118
5.6.12 Verify Mode..........................................................................................................118
5.6.13 DMA Request Deassertion ..................................................................................118
5.6.14 SYNC Field / LDRQ# Rules .................................................................................119
8254 Timers (D31:F0).......................................................................................................120
5.7.1
5.7.2
8259 Interrupt Controllers (PIC) (D31:F0) ........................................................................123
5.8.1
5.8.2
5.8.3
5.8.4
Channel Priority ...................................................................................................110
5.5.1.1
5.5.1.2
Address Compatibility Mode ................................................................................110
Summary of DMA Transfer Sizes ........................................................................111
5.5.3.1
Autoinitialize.........................................................................................................111
Software Commands ...........................................................................................112
5.5.5.1
5.5.5.2
5.5.5.3
PCI DMA Expansion Protocol ..............................................................................113
PCI DMA Expansion Cycles ................................................................................114
DMA Addresses ...................................................................................................115
DMA Data Generation .........................................................................................115
DMA Byte Enable Generation..............................................................................115
DMA Cycle Termination .......................................................................................116
LPC DMA .............................................................................................................116
Asserting DMA Requests.....................................................................................116
Abandoning DMA Requests ................................................................................117
Timer Programming .............................................................................................120
Reading from the Interval Timer ..........................................................................121
5.7.2.1
5.7.2.2
5.7.2.3
Interrupt Handling ................................................................................................124
5.8.1.1
5.8.1.2
5.8.1.3
Initialization Command Words (ICWx) .................................................................125
5.8.2.1
5.8.2.2
5.8.2.3
5.8.2.4
Operation Command Words (OCW) ....................................................................126
Modes of Operation .............................................................................................126
5.8.4.1
5.8.4.2
5.8.4.3
5.8.4.4
5.8.4.5
Fixed Priority ........................................................................................110
Rotating Priority ...................................................................................110
Address Shifting When Programmed for 16-Bit
I/O Count by Words .............................................................................111
Clear Byte Pointer Flip-Flop.................................................................112
DMA Master Clear ...............................................................................112
Clear Mask Register ............................................................................112
Simple Read ........................................................................................122
Counter Latch Command.....................................................................122
Read Back Command..........................................................................122
Generating Interrupts ...........................................................................124
Acknowledging Interrupts.....................................................................124
Hardware/Software Interrupt Sequence...............................................125
ICW1 ....................................................................................................125
ICW2 ....................................................................................................126
ICW3 ....................................................................................................126
ICW4 ....................................................................................................126
Fully Nested Mode ...............................................................................126
Special Fully-Nested Mode ..................................................................127
Automatic Rotation Mode (Equal Priority Devices) ..............................127
Specific Rotation Mode (Specific Priority)............................................127
Poll Mode .............................................................................................127
Contents
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