FW82801EB Intel, FW82801EB Datasheet - Page 74

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FW82801EB

Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801EB

Lead Free Status / RoHS Status
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74
Table 28. Power Plane and States for Output and I/O Signal (Sheet 3 of 3)
®
ICH5 Power Planes and Pin States
SMBCLK, SMBDATA
NOTES:
Signal Name
LINKALERT#
1. ICH5 sets these signals at reset for processor frequency strap.
2. GPIO18 will toggle at a frequency of approximately 1 Hz when the ICH5 comes out of reset
3. CPUPWRGD is an open-drain output that represents a logical AND of the ICH5’s VRMPWRGD and PWROK
4. The states of main I/O signals are taken at the times During PCIRST# and Immediately after PCIRST#.
5. The states of resume I/O signals are taken at the times During RSMRST# and Immediately after RSMRST#.
6. GPIO48 is an open-drain output. During boot, or during a hard reset with power cycling, GPIO48 will be
SMLINK[1:0]
GPIO[17:16]
GPIO[20:19]
GPIO[28:27]
AC_SDOUT
AC_SYNC
AC_RST#
GPIO48
GPIO49
GPIO18
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO32
GPIO34
signals, and thus will be driven low by ICH5 when either VRMPWRGD or PWROK are inactive. During boot,
or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low to High-Z.
expected to transition from low to High-Z.
SPKR
Resume I/O
Resume I/O
Resume I/O
Resume I/O
Resume I/O
Resume I/O
Resume I/O
Main I/O
Main I/O
Main I/O
Main I/O
Main I/O
CPU I/O
Main I/O
Main I/O
Main I/O
Main I/O
Main I/O
Main I/O
Main I/O
Power
Plane
System Management Interface
Internal Pull-
Internal Pull-
PCIRST#
RSMRST#
Unmultiplexed GPIO Signals
High-Z with
See Note 6
Low with
Multiplexed GPIO Signals
During
High-Z
High-Z
High-Z
High-Z
Down
Miscellaneous Signals
High
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Up
SMBus Interface
AC ’97 Interface
4
5
/
after PCIRST#
Intel
Immediately
RSMRST#
See Note 2
Running
Running
High-Z
High-Z
High-Z
High-Z
High-Z
High
High
High
High
High
High
High
High
High
®
Low
Low
Low
82801EB ICH5 / 82801ER ICH5R Datasheet
5
4
/
Cold Reset
Bit (High)
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
Defined
High-Z
High
High
Low
Low
S1
Defined
Defined
Defined
Defined
Defined
Defined
Low
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
S3
Defined
Defined
Defined
Defined
Defined
Defined
S4/S5
Low
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off

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