FW82801EB Intel, FW82801EB Datasheet - Page 80

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.1.2
5.1.3
5.1.4
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Note: If the processor issues a locked cycle to a resource that is too slow (e.g., PCI), the ICH5 does not
Note: Locked cycles are assumed to be rare. Locks by PCI targets are assumed to exist for a short
allow upstream requests to be performed until the cycle completes. This may be critical for
isochronous buses that assume certain timing for their data flow (e.g., AC ’97 or USB). Devices on
these buses may suffer from underrun if the asynchronous traffic is too heavy. Underrun means that
the same data is sent over the bus while ICH5 is not able to issue a request for the next data. Snoop
cycles are not permitted while the front side bus is locked.
duration (a few microseconds at most). If a system has a very large number of locked cycles and
some that are very long, the system will definitely experience underruns and overruns. The units
most likely to have problems are the AC ’97 controller and the USB controllers. Other units could
get underruns/overruns, but are much less likely. The IDE controller (due to its stalling capability
on the cable) should not get any underruns or overruns.
PCI-to-PCI Bridge Model
From a software perspective, the ICH5 contains a PCI-to-PCI bridge. This bridge connects the hub
interface to the PCI bus. By using the PCI-to-PCI bridge software model, the ICH5 can have its
decode ranges programmed by existing plug-and-play software such that PCI ranges do not
conflict with AGP and graphics aperture ranges in the Host controller.
IDSEL to Device Number Mapping
When addressing devices on the external PCI bus (with the PCI slots), the ICH5 asserts one address
signal as an IDSEL. When accessing device 0, the ICH5 asserts AD16. When accessing Device 1,
the ICH5 asserts AD17. This mapping continues all the way up to device 15 where the ICH5
asserts AD31. Note that the ICH5’s internal functions (AC ’97, IDE, USB, SATA and PCI Bridge)
are enumerated like they are on a separate PCI bus (the hub interface) from the external PCI bus.
The integrated LAN controller is Device 8 on the ICH5’s PCI bus, and hence it uses AD24 for
IDSEL.
SERR# Functionality
There are several internal and external sources that can cause SERR#. The ICH5 can be
programmed to cause an NMI based on detecting that an SERR# condition has occurred. The NMI
can also be routed to instead cause an SMI#. Note that the ICH5 does not drive the external PCI bus
SERR# signal active onto the PCI bus. The external SERR# signal is an input into the ICH5 driven
only by external PCI devices. The conceptual logic diagrams in
sources of SERR#, along with their respective enable and status bits.
error reporting logic is configured for NMI# generation.
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Figure 5
Figure 7
and
Figure 6
shows how the ICH5
illustrate all