FW82801EB Intel, FW82801EB Datasheet - Page 82

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.1.5
82
Figure 7. NMI# Generation Logic
Note: The HP_Unsupported bit (D30:F0:40h bit 20) must be cleared for any of the parity checking enable
Note: If NMIs are enabled, and parity error checking on PCI is also enabled, then parity errors will cause
Parity Error Detection
The ICH5 can detect and report different parity errors in the system. The ICH5 can be programmed
to cause an NMI (or SMI# if NMI is routed to SMI#) based on detecting a parity error. The
conceptual logic diagram in
with their respective enable bits, status bits, and the results.
For hub interface-to-PCI data packets, with MCH’s that generate HI parity, the ICH5 provides the
ability to generate bad parity on all data driven by the ICH5 when bad data parity was detected on
hub interface. This prevents PCI agents that are capable of checking parity from taking corrupted
data unknowingly. This state can be entered due to either hub interface-to-PCI write data or hub
interface-to-PCI read completion data. This mode is enabled by D30.F0.50h.bit 19 and reported in
D30.F0.92h.bit 0.
bits to have any effect.
an NMI. Some operating systems will not attempt to recover from this NMI, since it considers the
detection of a PCI error to be a catastrophic event.
IOCHK From SERIRQ Logic
D30:F0 PDSTS
D30:F0 SECSTS
during LPC or Legacy DMA
[PCI_SERR_EN]
PCI Parity Error detected
during AC'97, IDE or USB
PCI Parity Error detected
D30:F0 BRIDGE_CNT
[Parity Error Response
[SSE]
[Parity Error Response]
NMI_SC
[SSE]
Master Cycle
Hub Interface Parity
Master Cycle
[IOCHK_NMI_EN]
D30:F0 CMD
D31:F0 PCICMD
Error Detected
Enable]
NMI_SC
[PER]
Figure 7
OR
AND
AND
AND
details all the parity errors that the ICH5 can detect, along
[HUBNMI_STS]
AND
TCO1_STS
[NMI_NOW]
TCO1_CNT
AND
D30:F0 SECSTS
[SERR#_NMI_STS]
[DPD]
D31:F0 PCISTA
D30:F0 PD_STS
[IOCHK_NMI_STS]
NMI_SC
Intel
[DPED]
[DPD]
NMI_SC
®
OR
82801EB ICH5 / 82801ER ICH5R Datasheet
OR
[NMI_EN]
NMI_EN
OR
AND
To NMI#
Output
Gating
Logic
and