FW82801EB Intel, FW82801EB Datasheet - Page 84

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.1.7
5.2
84
PCI Dual Address Cycle (DAC) Support
The ICH5 supports Dual Address Cycle (DAC) format on PCI for cycles from PCI initiators to
main memory. This allows PCI masters to generate an address up to 44 bits. The size of the actual
supported memory space is determined by the memory controller and the processor.
The DAC mode is only supported for PCI adapters and USB EHC, and is not supported for any of
the internal PCI masters (IDE, LAN, USB UHC, AC ’97, 8237 DMA, etc.).
When a PCI master wants to initiate a cycle with an address above 4 G, it follows the following
behavioral rules (See PCI Local Bus Specification, Revision 2.3, Section 3.9 for more details):
LAN Controller (B1:D8:F0)
The ICH5’s integrated LAN controller includes a 32-bit PCI controller that provides enhanced
scatter-gather bus mastering capabilities and enables the LAN controller to perform high-speed
data transfers over the PCI bus. Its bus master capabilities enable the component to process high
level commands and perform multiple operations; this lowers processor utilization by off-loading
communication tasks from the processor. Two large transmit and receive FIFOs of 3 KB each help
prevent data underruns and overruns while waiting for bus accesses. This enables the integrated
LAN controller to transmit data with minimum interframe spacing (IFS).
The ICH5 integrated LAN controller can operate in either full-duplex or half-duplex mode. In full-
duplex mode the LAN controller adheres with the IEEE 802.3x Flow Control Specification. Half
duplex performance is enhanced by a proprietary collision reduction mechanism.
The integrated LAN controller also includes an interface to a serial (4-pin) EEPROM. The
EEPROM provides power-on initialization for hardware and software configuration parameters.
From a software perspective, the integrated LAN controller appears to reside on the secondary side
of the ICH5’s virtual PCI-to-PCI bridge (see
assigned a different number, depending upon system configuration.
1. On the first clock of the cycle (when FRAME# is first active), the peripheral uses the DAC
2. Also during the first clock, the peripheral drives the AD[31:0] signals with the low address.
3. On the second clock, the peripheral drives AD[31:0] with the high address. The address is
4. The rest of the cycle proceeds normally.
encoding on the C/BE# signals. This unique encoding is: 1101.
right justified: A[43:32] appear on AD[12:0]. The value of AD[31:13] is expected to be 0;
however, the ICH5 ignores these bits. C/BE# indicate the bus command type (memory read,
memory write, etc.)
Section
Intel
®
5.1.2). This is typically Bus 1, but may be
82801EB ICH5 / 82801ER ICH5R Datasheet