FW82801EB Intel, FW82801EB Datasheet - Page 89

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: The LAN controller reports a system error for any error during an address phase, whether or not it
Write Accesses: The processor, as the initiator, drives the address lines AD[31:0], the command
and byte enable lines C/BE[3:0]# and the control lines IRDY# and FRAME#. It also provides the
LAN controller with valid data on each data access immediately after asserting IRDY#. The LAN
controller controls the TRDY# signal and asserts it from the data access. The LAN controller
allows the processor to issue only one I/O write cycle to the Control/Status Registers, generating a
disconnect by asserting the STOP# signal. This is true for both memory mapped and I/O mapped
accesses.
Retry Premature Accesses
The LAN controller responds with a Retry to any configuration cycle accessing the LAN controller
before the completion of the automatic read of the EEPROM. The LAN controller may continue to
Retry any configuration accesses until the EEPROM read is complete. The LAN controller does
not enforce the rule that the retried master must attempt to access the same address again in order to
complete any delayed transaction. Any master access to the LAN controller after the completion of
the EEPROM read is honored.
Error Handling
Data Parity Errors: The LAN controller checks for data parity errors while it is the target of the
transaction. If an error was detected, the LAN controller always sets the Detected Parity Error bit in
the PCI Configuration Status register, bit 15. The LAN controller also asserts PERR#, if the Parity
Error Response bit is set (PCI Configuration Command register, bit 6). The LAN controller does
not attempt to terminate a cycle in which a parity error was detected. This gives the initiator the
option of recovery.
Target-Disconnect: The LAN controller prematurely terminate a cycle in the following cases:
System Error: The LAN controller reports parity error during the address phase using the SERR#
pin. If the SERR# Enable bit in the PCI Configuration Command register or the Parity Error
Response bit are not set, the LAN controller only sets the Detected Parity Error bit (PCI
Configuration Status register, bit 15). If SERR# Enable and Parity Error Response bits are both set,
the LAN controller sets the Signaled System Error bit (PCI Configuration Status register, bit 14) as
well as the Detected Parity Error bit and asserts SERR# for one clock.
The LAN controller, when detecting system error, claims the cycle if it was the target of the
transaction and continues the transaction as if the address was correct.
is involved in the current transaction.
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After accesses to its CSR
After accesses to the configuration space
Functional Description
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