ISP1183BS STEricsson, ISP1183BS Datasheet - Page 30

• Manufacturer Part Number: ISP1183BS
• Manufacturer: STEricsson

Specifications of ISP1183BS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 20.
ISP1183_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Hardware Configuration register: bit allocation
12.1.5 Interrupt Enable register (R/W: C3h/C2h)
reserved
DAKOLY
R/W
R/W
15
0
7
0
Table 21.
This command individually enables or disables interrupts from all endpoints, as well as
interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend, resume,
reset). A bus reset will not change any of the programmed bit values.
The command accesses the Interrupt Enable register that consists of 4 bytes. The bit
allocation is given in
Code: C2h/C3h — write or read Interrupt Enable register
Bit
15
14
13
12
11 to 8
7
6
5
4
3
2
1
0
DRQPOL
EXTPUL
R/W
R/W
14
0
6
1
Symbol
-
EXTPUL
-
CLKRUN
-
DAKOLY
DRQPOL
DAKPOL
reserved
WKUPCS
-
INTLVL
reserved
Hardware Configuration register: bit description
reserved
DAKPOL
R/W
R/W
13
1
5
0
Table
Description
reserved
Logic 1 indicates that an external 1.5 kΩ pull-up resistor is used on pin DP
and that SoftConnect is not used. Bus reset value: unchanged.
reserved
Logic 1 indicates that internal clocks are always running, even during the
suspend state. Logic 0 switches off the internal oscillator and PLL, when
they are not needed. During the suspend state, this bit must be made
logic 0 to meet suspend current requirements. The clock is stopped after a
delay of approximately 2 ms, following the setting of bit GOSUSP in the
Mode register. Bus reset value: unchanged.
reserved
Logic 1 selects DACK-only DMA mode. Logic 0 selects 8237 compatible
DMA mode. Bus reset value: unchanged.
Selects the DREQ signal polarity (0 = active LOW, 1 = active HIGH). Bus
reset value: unchanged.
Selects the DACK signal polarity (0 = active LOW, 1 = active HIGH). Bus
reset value: unchanged.
This bit should be always written as logic 0.
Logic 1 enables remote wake-up through a LOW level on input CS_N (For
wake-up on CS_N to work, V
unchanged.
reserved
Selects interrupt signaling mode on output INT_N (0 = level, 1 = pulsed). In
pulsed mode, an interrupt produces 166 ns pulse. For details, see
Section
This bit should be always written as logic 0.
Rev. 03 — 20 January 2009
22.
11. Bus reset value: unchanged.
CLKRUN
reserved
R/W
R/W
12
0
4
0
Low-power USB Peripheral Controller with DMA
WKUPCS
R/W
R/W
11
0
3
0
BUS
must be present). Bus reset value:
reserved
R/W
R/W
10
0
2
1
reserved
© ST-NXP Wireless 2009. All rights reserved.
INTLVL
R/W
R/W
9
1
1
0
ISP1183
reserved
R/W
R/W
8
1
0
0
29 of 65