ISP1183BS STEricsson, ISP1183BS Datasheet - Page 37

• Manufacturer Part Number: ISP1183BS
• Manufacturer: STEricsson

Specifications of ISP1183BS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 32.
[1]
ISP1183_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
DMA Configuration register: bit allocation
12.3.2 DMA Configuration register (R/W: F1h/F0h)
12.3.3 DMA Counter register (R/W: F3h/F2h)
CNTREN
R/W
R/W
0
0
15
[1]
7
[1]
This command defines the DMA configuration of the ISP1183 and enables or disables
DMA transfers. The command accesses the DMA Configuration register, which consists
of 2 bytes. The bit allocation is given in
disabled), all other bits remain unchanged.
Code: F0h/F1h — write or read DMA Configuration
Transaction — write or read 2 bytes
Table 33.
This command accesses the DMA Counter register, which consists of 2 bytes. The bit
allocation is given in
transfer. Reading the register returns the number of remaining bytes in the current
transfer. A bus reset will not change programmed bit values.
Bit
15
14
13 to 8
7 to 4
3
2
1 to 0
SHORTP
R/W
R/W
0
0
14
[1]
6
[1]
EPDIX[3:0]
Symbol
CNTREN
SHORTP
-
EPDIX[3:0]
DMASTART
-
BURSTL[1:0] Selects the DMA burst length:
DMA Configuration register: bit description
R/W
R/W
0
13
0
5
[1]
[1]
Table
Rev. 03 — 20 January 2009
Description
Logic 1 enables the generation of an EOT condition, when the DMA
Counter register reaches zero. Bus reset value: unchanged.
Logic 1 enables short or empty packet mode. When receiving (OUT
endpoint) a short or empty packet, an EOT condition is generated. When
transmitting (IN endpoint), this bit should be cleared. Bus reset value:
unchanged.
reserved
Indicates the destination endpoint for DMA, see
Writing logic 1 starts a DMA transfer. Logic 0 forces the end of an
ongoing DMA transfer. Reading this bit indicates whether DMA is started
(0 = DMA stopped, 1 = DMA started). This bit is cleared by a bus reset.
reserved
00 — single-cycle mode (1 byte)
01 — burst mode (4 bytes)
10 — burst mode (8 bytes)
11 — burst mode (16 bytes)
Bus reset value: unchanged.
34. Writing to the register sets the number of bytes for a DMA
R/W
R/W
0
12
0
4
[1]
[1]
Low-power USB Peripheral Controller with DMA
Table
START
R/W
DMA
R/W
0
11
[1]
3
0
32. A bus reset will clear bit DMAEN (DMA
reserved
reserved
R/W
R/W
0
10
2
0
[1]
Table
© ST-NXP Wireless 2009. All rights reserved.
R/W
R/W
0
0
9
1
[1]
[1]
BURSTL[1:0]
7.
ISP1183
R/W
R/W
0
0
8
[1]
0
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