LSISAS1068 LSI, LSISAS1068 Datasheet

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LSISAS1068

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LSISAS1068
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TECHNICAL
MANUAL
LSISAS1068 PCI-X to
8-Port Serial Attached
SCSI/SATA Controller
O c t o b e r 2 0 0 5
Version 2.1
®
DB14-000287-04

Related parts for LSISAS1068

LSISAS1068 Summary of contents

Page 1

... TECHNICAL MANUAL LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller Version 2.1 ® DB14-000287-04 ...

Page 2

... I C standard Specification as defined by Philips. Document DB14-000287-04, Version 2.1 (October 2005) This document describes LSI Logic Corporation’s LSISAS1068 Serial Attached SCSI/SATA Controller and will remain the official reference source for all revisions/releases of this product until rescinded by an update. ...

Page 3

... Preface This book is the primary reference and technical manual for the LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller. It contains a complete functional description for the LSISAS1068, as well as the physical and electrical specifications for the LSISAS1068. Audience This document assumes that you are familiar with microprocessors and related support devices. The people who benefi ...

Page 4

... Appendix A, Register LSISAS1068. Appendix B, Reference that may benefit the reader. Related Publications LSI Logic Documents Fusion-MPT™ Device Management User’s Guide, Version 2.0, DB15-000186-02 LSI Logic World Wide Web Home Page www.lsilogic.com ANSI 11 West 42nd Street New York, NY 10036 ...

Page 5

... Preliminary Release. Modified text regarding IM and IS drive sup- port (page 1-4); identified throughout the Manual that the LSISAS1068 PCI interface is not tolerant of 5V PCI; corrected typo on page 3-2 regarding 636 Ball Grid Array; changed accu- racy requirement for Reference Clock signal to +/- 50ppm (Table 3.9) ...

Page 6

... Preface Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...

Page 7

... Introduction 1.1 General Description 1.2 Benefits of SAS 1.3 Benefits of the Fusion-MPT Architecture 1.4 Benefits of PCI-X 1.5 Benefits of GigaBlaze Transceivers 1.6 Summary of LSISAS1068 Features 1.6.1 1.6.2 1.6.3 1.6.4 1.6.5 1.6.6 1.6.7 1.6.8 Chapter 2 Functional Description 2.1 Block Diagram Description 2 ...

Page 8

... Chapter 5 Specifications 5.1 DC Characteristics 5.2 AC Characteristics viii Contents Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Memory Requirements Flash ROM Controller NVSRAM Controller PCI System Signals PCI Address and Data Signals PCI Interface Control Signals PCI Arbitration Signals ...

Page 9

... External Memory Timing Diagrams 5.4 Pinout 5.5 Package Drawings Appendix A Register Summary Appendix B Reference Specifications Index Customer Feedback Contents Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. 5-11 5-14 5-21 ix ...

Page 10

... Contents Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...

Page 11

... Narrow and Wide Links 2.4 SSP, STP, and SMP Protocol Usage 2.5 Flash ROM Block Diagram 2.6 NVSRAM Block Diagram 2.7 ZCR Circuit Diagram for the LSISAS1068 3.1 LSISAS1068 Functional Signal Grouping 5.1 External Clock 5.2 Reset Input 5.3 Interrupt Output 5 ...

Page 12

... Contents Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...

Page 13

... Test and JTAG Signals 3.15 Power and Ground Signals 3.16 Power-On Sense Pin Definitions 3.17 Pull-Up and Pull-Down Conditions 4.1 LSISAS1068 PCI Configuration Space Address Map 4.2 Multiple Message Enable Field Bit Encoding 4.3 BIR Field Definitions 4.4 Maximum Outstanding Split Transactions 4.5 Maximum Memory Read Count 4 ...

Page 14

... Listing by Signal Name 5.31 Listing by Pin Number A.1 LSISAS1068 PCI Configuration Space Registers A.2 LSISAS1068 PCI I/O Space Registers A.3 LSISAS1068 PCI Memory [0] Space Registers B.1 Reference SpecifIcations xiv Contents Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. 5-4 5-4 ...

Page 15

... LSISAS1068 integrates eight high-performance SAS/SATA phys and a 64-bit, 133 MHz PCI-X bus master DMA core. Each of the eight phys on the LSISAS1068 is capable of 3.0 Gbit/s and 1.5 Gbit/s SAS link rates, and 3.0 Gbit/s and 1.5 Gbit/s SATA link rates. The LSISAS1068 supports the SAS protocol as described in the Serial Attached SCSI Standard, version 1 ...

Page 16

... LSI Logic produces the LSISAS1068 using the Gflx Each port on the LSISAS1068 supports SAS and SATA devices using the SAS Serial SCSI Protocol (SSP), Serial Management Protocol (SMP), Serial Tunneling Protocol (STP), and SATA. The SSP protocol enables communication with other SAS devices ...

Page 17

... SAS/SATA Device SAS/SATA Device 64-Bit, 133 MHz SAS/SATA Device SAS/SATA Device PCI/PCI-X Interface Figure 1.2 LSISAS1068 Controller and LSISASx12 Expander Example Application PCI/PCI-X Interface LSISAS1068 LSISASx12 SAS/SATA SAS/SATA Drives Drives General Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...

Page 18

... PBSRAM devices. Most configurations use a flash ROM to store firmware, configuration information, and persistent data information. The LSISAS1068 supports the Integrated RAID solution, which is a highly integrated, low cost RAID implementation designed for systems requiring redundancy and high availability, but not needing a full- featured RAID implementation ...

Page 19

... ATA firmware. The LSISAS1068 can function as an SSP initiator, an SSP target, an SMP initiator, an STP initiator SATA initiator. The LSISAS1068 uses SSP to communicate with other SAS devices, and uses SMP to communicate topology management information with other SAS devices. ...

Page 20

... The Fusion-MPT architecture improves overall system performance by requiring only a thin device driver, which off loads the intensive work of managing I/Os from the system processor to the LSISAS1068. The use of thin, easy to develop, common OS device drivers accelerates time to market by reducing device driver development and certification times. ...

Page 21

... The LSISAS1068 supports 133 MHz, 64-bit PCI-X bus and is backwards compatible with previous versions of the PCI/PCI-X specification. Per the PCI-X addendum, the LSISAS1068 includes transaction information with all PCI-X transactions to enable more effi ...

Page 22

... Summary of LSISAS1068 Features This section provides a summary of the LSISAS1068 features and benefits. It contains information on Performance, Integration, Usability, Flexibility, Reliability, and Testability. 1.6.1 SAS Features This section describes the SAS features. Provides 8 fully independent phys Each phy supports 3.0 Gbit/s and 1.5 Gbit/s SAS data transfers ...

Page 23

... Memory Read Multiple commands Supports the PCI-X Memory Read Dword, Split Completion, Memory Read Block, Memory Write Block commands Summary of LSISAS1068 Features Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Operates up to 133 MHz PCI-X Operates at 33 MHz or 66 MHz PCI ...

Page 24

... Integration These features make the LSISAS1068 easy to integrate: Supports backwards compatibility with previous revisions of the PCI specification, with the exception that the LSISAS1068 does not support 5 V PCI Provides a full 32-bit or 64-bit PCI-X DMA bus master Reduces time to market with the Fusion-MPT architecture – ...

Page 25

... Allows grouping phys within a single quad port to form a wide port Allows programming of the World Wide Name 1.6.7 Reliability These features enhance the reliability of the LSISAS1068. Uses proven GigaBlaze transceivers Provides ESD protection Provides latch-up protection Has a high proportion of power and ground pins ...

Page 26

... Introduction Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...

Page 27

... Chapter 2 Functional Description This chapter provides a subsystem level overview of the LSISAS1068, a discussion of the Fusion-MPT architecture, and a functional description of the LSISAS1068 interfaces. This chapter contains the following sections: Section 2.1, “Block Diagram Description” Section 2.2, “Fusion-MPT Architecture Overview” Section 2.3, “PCI Functional Description” ...

Page 28

... Block Diagram Description The LSISAS1068 consists of three major modules and a context RAM. The three major modules are the host interface module and the two Quad Port modules. The modules consist of the following components: Host Interface Module – – – – ...

Page 29

... Figure 2.1 LSISAS1068 Controller Block Diagram Host Interface Module PCI-X 133 MHz TimerConfig PCI/PCI-X Interface DMA Arbiter System Interface ICE I/F AHB Arbiter IOP (ARM966) IRQ Controller GPIO/LED TimerConfig SIO A SIO A SIO B SIO B UART UART XMEM Bus External Memory ...

Page 30

... The LSISAS1068 provides a PCI-X interface that supports 64-bit, 133 MHz PCI-X bus. The interface is backward compatible with previous implementations of the PCI specification, with the exception that the LSISAS1068 does not support 5 V PCI. For more information on the PCI interface, refer to 2.1.1.2 ...

Page 31

... Timer and Configuration This block supports the LSISAS1068 LED and GPIO interfaces. There are a total of 17 LED signals on the LSISAS1068. Each of the eight phys has an LED signal to indicate activity on the link and an LED signal to indicate an error on the link. The GPIO interface contains four independent GPIO signals. This block provides a fi ...

Page 32

... The UART provides test and debug access to the LSISAS1068. 2.1.2 Quad Port The Quad Port modules in the LSISAS1068 implement the SSP, SMP, and STP/SATA protocols, and manage the eight SAS/SATA phys. Each Quad Port module supports four SAS/SATA phys. The following subsections describe the Quad Port modules. Refer to Functional Description,” ...

Page 33

... SAS Link and Phy The LSISAS1068 uses the Gflx GigaBlaze transceivers to implement the SAS link. The SAS link layer manages SAS connections between initiator and target ports, data clocking, and CRC checking on received data. The SAS link is also responsible for starting a link reset sequence. ...

Page 34

... There are two, 32-bit message queues: the request message queue and the reply message queue. The host uses the request queue to request an action by the LSISAS1068, and the LSISAS1068 uses the reply queue to return status information to the host. The request message queue consists of the request post FIFO. The reply message queue consists of both the reply post FIFO and the reply free FIFO ...

Page 35

... The host PCI interface complies with the PCI Local Bus Specification, Version 3.0 and the PCI-X Addendum to the PCI Local Bus Specification, Revision 2.0. The LSISAS1068 supports a 133 MHz, 64-bit PCI-X bus. The LSISAS1068 provides support for 64-bit addressing with Dual Address Cycle (DAC) ...

Page 36

... IDSEL is not asserted. Bits AD[10:8] address the PCI Function Configuration Space (AD[10:8] = 0b000). The LSISAS1068 does not respond to any other encodings of AD[10:8]. Bits AD[7:2] select one of the 64 Dword registers in the device’s PCI Configuration Space. Bits AD[1:0] determine if the confi ...

Page 37

... The LSISAS1068 ignores reserved commands as a slave and never generates them as a master. 2. When acting as a slave in the PCI mode, the LSISAS1068 supports this command as the PCI Memory Read command. 3. When acting as a slave in the PCI mode, the LSISAS1068 supports this command as the PCI Memory Write command. PCI Functional Description Copyright © ...

Page 38

... PCI or PCI-X bus mode. 2.3.2.5 Memory Read Command The LSISAS1068 uses the Memory Read command to read data from an agent mapped in the memory address space. The target can perform an anticipatory read if such a read produces no side effects. The LSISAS1068 supports this command when operating in the PCI bus mode ...

Page 39

... The LSISAS1068 supports this command when operating in the PCI-X bus mode. 2.3.2.7 Memory Write Command The Memory Write command writes data to an agent mapped in the memory address space. The target assumes responsibility for data coherency when it returns “ready.” The LSISAS1068 supports this command when operating in either the PCI or PCI-X bus mode ...

Page 40

... Burst Size Selection – The Read Multiple command reads multiple cache lines of data during a single bus ownership. The number of cache lines the LSISAS1068 reads is a multiple of the cache line size, which Revision 3.0 of the PCI specification provides. The LSISAS1068 selects the largest multiple of the cache line size based on the amount of data to transfer ...

Page 41

... Alignment – The LSISAS1068 uses the calculated line size value to determine if the current address aligns to the cache line size. If the address does not align, the LSISAS1068 bursts data using a noncache command. If the starting address aligns, the LSISAS1068 issues a Memory Write and Invalidate command using the cache line size as the burst size. Multiple Cache Line Transfers – ...

Page 42

... LSISAS1068 selects the largest multiple of the cache line size based on the transfer size. When the DMA buffer contains less data than the value Cache Line Size Write command on the next cache boundary to complete the data transfer. 2.3.2.18 Memory Write Block Command The LSISAS1068 uses this command to burst data to memory ...

Page 43

... D3 2.4 SAS Functional Description The LSISAS1068 provides eight SAS/SATA phys. Each phy can form one side of the physical link in a connection with a phy on a different SAS/SATA device. The physical link contains four wires that form two differential signal pairs ...

Page 44

... Gbit/s SAS, increasing the number of phys in a port increases the data transfer rate. Combining four phys on the LSISAS1068 into a wide port enables bandwidths 12.0 Gbits/s. A link between two narrow ports is a narrow link. A link between two wide ports is a wide link ...

Page 45

... TX Phy TX Phy Each phy on the LSISAS1068 can function as an SSP Initiator, an SSP target, an SMP initiator, an STP initiator SATA Initiator. A phy can function in only one role during a connection, but function in different roles during different connections. The LSISAS1068 uses SSP to communicate with other SAS devices, and uses SMP to communicate management information with other SAS devices ...

Page 46

... AHB bus and an external 32-bit memory interface. This interface is for accessing external flash ROM and NVSRAM devices. Because the LSISAS1068 uses a 32-bit multiplexed address/data bus, designs using the LSISAS1068 do not require latches or CPLD devices to construct memory addresses. 2.5.1 ...

Page 47

... The LSISAS1068 flash ROM interface provides access to nonvolatile code and parameter storage for both the embedded ARM core and the host system. An 8-bit wide flash ROM is optional if the LSISAS1068 is not the boot device, and a suitable driver exists to initialize the LSISAS1068 and download its code. The flash ROM interface: uses an 8-bit data bus reads 4 bytes from the fl ...

Page 48

... LSISAS1068 performs the instruction located at flash ROM address 0x000000. If the signature values do not match, the LSISAS1068 records an error and ignores the flash ROM instruction. The flash ROM signature does not include the first 3 bytes of flash ROM memory because these bytes contain a branch offset instruction. ...

Page 49

... NVSRAM and returns the resulting 32-bit Dword for each AHB Dword read request Byte lane 3 of the LSISAS1068 external memory bus (MAD[31:24]) connects to the 8-bit data bus of the NVSRAM. BWE[2]/ provides the write enable signal for the NVSRAM. The MOE[0]/ signal enables the attached NVSRAM to drive data. NVSRAM confi ...

Page 50

... LSISAS1068 responds to PCI configuration cycles when the ALT_GNT/ signal is asserted. Connect the ALT_GNT/ pin on the LSISAS1068 to the PCI GNT/ signal of the external I/O processor. This allows the I/O processor to perform PCI configuration cycles to the LSISAS1068 when the I/O processor is granted the PCI bus. This confi ...

Page 51

... Int B/ Int C/ Int D/ AD21 AD19 Note: To maintain proper interrupt mapping, select the address line for use as IDSEL on the LSISAS1068 address lines above IDSEL on ZCR slot. 2.7 Universal Asynchronous Receiver/Transmitter (UART) The LSISAS1068 provides an industry standard UART interface. The UART performs serial-to-parallel conversion on data characters received from a peripheral device or modem, and parallel-to-serial conversion on data characters received from the CPU ...

Page 52

... ICE JTAG post. The header has a 100 mil spacing between posts. The connector is a 20-way header that mates with IDC sockets that are mounted on a ribbon cable. This header enables LSI Logic to debug the board design. to include a header, route the ARM Multi-ICE signals to through-holes. ...

Page 53

... Chapter 3 Signal Description This chapter describes the input and output signals of the LSISAS1068, and consists of the following sections: Section 3.1, “Signal Organization” Section 3.2, “PCI Signals” Section 3.3, “PCI-Related Signals” Section 3.4, “CompactPCI Signals” Section 3.5, “SAS Signals” ...

Page 54

... Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Input, a standard input-only signal Output, a standard output driver (typically a Totem Pole Input and output (bidirectional) Power Ground contains the functional signal groupings of the LSISAS1068. and Table 5.31 on page 5-14 on page 5-22 ...

Page 55

... Figure 3.1 LSISAS1068 Functional Signal Grouping System Address and Data PCI/PCI-X Interface Bus Control Interface Arbitration Error Reporting Interrupt PCI-Related Signals Compact PCI Interface SAS Interface Communication Interface Signal Organization Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. LSISAS1068 ...

Page 56

... PAR AC11 PAR64 AE19 3-4 Signal Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. describes the PCI system signals. Type Description I Refer to the PCI Local Bus Specification, Version 3.0, and the PCI-X Addendum to the PCI Local Bus Specification, I Version 2 ...

Page 57

... PERR/ AA10 SERR/ AE5 PCI Signals Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. describes the PCI interface control signals. Description I/O Refer to the PCI Local Bus Specification, Version 3.0, and the PCI-X Addendum to the PCI Local Bus Specification, I/O Version 2 ...

Page 58

... ZCR implementations. I The active LOW ZCR enable input configures the LSISAS1068 for Zero Channel RAID operation. When this input is asserted, the standard PCI signals INTA/ and GNT/ are not used, and the alternate signals ALT_INTA/ and ALT_GNT/ are used. When this input is deasserted, the chip is confi ...

Page 59

... Asserting active LOW CompactPCI Enable configures the LSISAS1068 for the CompactPCI protocol. I The active HIGH CompactPCI Switch signal indicates to the LSISAS1068 that a change in the system configuration is imminent. The CompactPCI device insertion/removal mechanism controls the assertion of this signal. I/O This signal informs the system of a board removal or insertion. ...

Page 60

... The Multiplexed Address/Data bus signals provide the address and data bus to the PBSRAM, flash ROM, and NVSRAM. These signals also provide Power-On Sense configuration functions to the LSISAS1068. Sense Pins Description,” configuration options. Provide pull-up resistors for these pins. ...

Page 61

... PBSRAMs. The LSISAS1068 supports up to four PBSRAMs in an interleaved and depth-expanded configuration. O Asserting the active LOW Flash Chip Select signal selects the flash ROM. The LSISAS1068 maps the flash ROM address space into system memory. 2 describes the I C and UART signals. ...

Page 62

... M6 SIO_END_A, C24, SIO_END_B L1 3-10 Signal Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. describes the SIO A and SIO B signals. Description O The Serial I/O Clock signals provide the clock signal for SIO A and SIO B, respectively. I The Serial I/O Data In A signal provides the data input signal to the SIO interface for Quad Port 0 ...

Page 63

... HB_LED/ M5 FSELA E3 Configuration and General Purpose Signals Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. describes the configuration and general purpose signals. I Asserting the Test Reset signal forces the chip into a Power-On-Reset state. This signal must be supplied by a power-on reset circuit on the board ...

Page 64

... F5 ECC[5:2] V5, AB1, W4, AC1 SPARE[3:2] E22, G20 RESERVED V4, W3 3-12 Signal Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. describes the test and JTAG signals. Description I JTAG Debug Clock. I JTAG Debug Reset. I JTAG Debug Test Data In. O JTAG Debug Test Data Out. ...

Page 65

... AD1, AD2, AD10, AD26, AE6, AE7, AE11, AE12, AE15, AE16, AE20, AE21, AF3, AF5, AF13, AF16, AF24 Power Signals Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. describes the power and ground signals. Type Description P These signals provide 1.2 V power. ...

Page 66

... F7, F8, A7, E11, E14, D16, G18, E19 TXB_VSS[7:0] D4, E8, F10, D11, F14, E16, B19, E20 3-14 Signal Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Type Description G These signals provide ground. G These signals provide ground for the GigaBlaze core of each respective phy. ...

Page 67

... Power-On Sense Pins Description This section discusses the power-on sense pin configuration options. For setting global operating conditions, the LSISAS1068 uses power-on sense register bits that source their data from the state of the memory address/data bus (MAD[31:0]) during the device boot up sequence. The MAD signals are 3-stated and read continuously during PCI reset, and are latched upon removal of the PCI reset signal ...

Page 68

... MAD[16], PCI-X Operation – Pulling this signal LOW enables the PCI-X operation. Pulling this signal HIGH disables PCI-X operation. 3-16 Signal Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Pulled LOW (Default) No NVSRAM/SRAM installed NVSRAM/SRAM installed SRAM Installed ...

Page 69

... Device ID register to 0b0. Pulling this signal HIGH programs bit 0 of the Device ID register to 0b1. MAD[2:1], Flash ROM Size – These pins configure the flash ROM size. Power-On Sense Pins Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Subsystem ID register description on 3-17 ...

Page 70

... B13 FSELA E3 TST_RST/ F6 3-18 Signal Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. describes the pull-up and pull-down signals for the LSISAS1068. Pull Type Internal Pull-down. Internal Pull-down. Internal Pull-up. Internal Pull-up. Internal Pull-up. Internal Pull-up. Internal Pull-up. ...

Page 71

... Management, Messaged Signaled Interrupts, MSI-X, and PCI-X) to optimize device performance. The LSISAS1068 does not hard code the location and order of the PCI extended capability structures. The address and location of the PCI extended capability structures are subject to change. To access a PCI LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller Copyright © ...

Page 72

... Capability Pointer registers and identify the extended capability structure with the Capability ID register for the given structure. Table 4.1 LSISAS1068 PCI Configuration Space Address Map 31 Device ID Status Class Code Reserved Header Type ...

Page 73

... The Command register provides coarse control over the PCI function’s ability to generate and respond to PCI cycles. Writing a zero to this register logically disconnects the LSISAS1068 PCI function from the PCI bus for all accesses except configuration accesses. Reserved This field is reserved. ...

Page 74

... Setting this bit enables the LSISAS1068 PCI function to detect parity errors on the PCI bus and report these errors to the system. Clearing this bit causes the LSISAS1068 PCI function to set the Detected Parity Error bit, bit 15 in the PCI Status register, but not assert PERR/ when the PCI function detects a parity error ...

Page 75

... Version 3.0, and PCI-X Addendum to the PCI Local Bus Specification, Revision 2.0. Signaled System Error The LSISAS1068 PCI function sets this bit when asserting the SERR/ signal. Received Master Abort (from Master) A master device sets this bit when a Master Abort command terminates its transaction (except for Special Cycle) ...

Page 76

... LSISAS1068 PCI function is capable of operating at 66 MHz. Pulling MAD[13] HIGH clears this bit and indicates to the host system that the LSISAS1068 PCI function is not configured to operate at 66 MHz. Refer to Section 3.12, “Power-On Sense Pins Description,” ...

Page 77

... New Capabilities The LSISAS1068 PCI function sets this read only bit to indicate a list of PCI extended capabilities such as PCI Power Management, MSI, MSI-X, and PCI-X support. Interrupt Status This bit reflects the status of the INTA/ (or ALT_INTA/) signal. Reserved This field is reserved. Register: 0x08 ...

Page 78

... The Latency Timer register specifies, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. If the LSISAS1068 initializes in the PCI mode, the default value of this register is 0x00. If the LSISAS1068 initializes in the PCI-X mode, the default value of this reg- ister is 0x40. ...

Page 79

... This base address register maps the operating register set into I/O Space. The LSISAS1068 requires 256 bytes of I/O Space for this base address register. Hardware sets bit 0 to 0b1. Bit 1 is reserved and returns 0b0 on all reads. PCI Configuration Space Register Description Copyright © ...

Page 80

... Memory Space [0] base address. Hardware programs bits [9:0] to 0b0000000100, which indicates that the Memory Space [0] base address is 64 bits wide and that the memory data is not prefetchable. The LSISAS1068 requires 1024 bytes of memory space. Register: 0x18–0x1B Memory [0] High ...

Page 81

... Memory Space [1] base address. Hardware programs bits [12:0] to 0b0000000000100, which indicates that the Memory Space [1] base address is 64 bits wide and that the memory data is not prefetchable. The LSISAS1068 requires 64 Kbytes of memory for Memory Space [1]. Register: 0x20–0x23 Memory [1] High ...

Page 82

... PCI device resides. This register provides a mechanism for an add-in card vendor to distinguish their cards from one another even if the cards use the same PCI controller (and have the same Vendor ID and Device ID). By default, the LSISAS1068 loads this register from the NVData at power up ...

Page 83

... ROM base address. The host system detects the size of the external memory by first writing 0xFFFFFFFF to this register and then reading the register back. The LSISAS1068 responds with zeros in all don’t care locations. The least significant one (1) that remains represents the binary version of the external memory size ...

Page 84

... PCI Host Register Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Expansion ROM Enable This bit controls if the device accepts accesses to its expansion ROM. Setting this bit enables address decoding. Depending on the system configuration, the device can optionally use an expansion ROM ...

Page 85

... PCI function presents interrupts on the INTA/ or ALT_INTA/ pins. The Interrupt Request Routing Mode bits, bits [9:8] in the mine if the function presents interrupts on INTA/, ALT_INTA/, or both. PCI Configuration Space Register Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Interrupt Line Interrupt Pin ...

Page 86

... Minimum Grant Min_Gnt This register specifies the desired settings for the latency timer values in units of 0.25 s. Min_Gnt specifies how long of a burst period the device needs. The LSISAS1068 sets this register to 0x40 indicating a burst period of 16.0 s. Maximum Latency Max_Lat This register specifi ...

Page 87

... D1_Support The PCI function sets this bit since the LSISAS1068 supports power management state D1. Aux_Current The PCI function clears this field since the LSISAS1068 does not support Aux_Current. Device Specific Initialization The PCI function clears this bit since no special initializa- tion is required before a generic class device driver can use it ...

Page 88

... PCI Host Register Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. PME Clock The LSISAS1068 clears this bit since the chip does not provide a PME pin. Version The PCI function programs these bits to 0b010 to indicate that the LSISAS1068 complies with the PCI Power Management Interface Specifi ...

Page 89

... Power Management Bridge Support Extensions Read Only 7 Power Management Bridge Support Extensions Power Management Bridge Support Extensions [7:0] This register indicates PCI Bridge specific functionality. The LSISAS1068 always returns 0x00 in this register. Register: 0xXX Power Management Data Read Only 7 Power Management Data ...

Page 90

... The PCI function sets this read only bit to indicate support of a 64-bit message address. Multiple Message Enable These read/write bits indicate the number of messages that the host allocates to the LSISAS1068. The host system software allocates all or a subset of the requested messages by writing to this field. The number of allocated 0 ...

Page 91

... LSISAS1068 requests from the host. The host system software reads this field to determine the number of requested messages. The number of requested messages must align to a power of two. The LSISAS1068 sets this field to 0b000 to request one message. All other encodings of this field are reserved. ...

Page 92

... MSI Message Upper Address The LSISAS1068 supports 64-bit MSI message. This register contains the upper 32 bits of the 64-bit message address, which the system specifies. The host system software can program this register to 0x0000 to force the PCI function to generate 32-bit message addresses. ...

Page 93

... MSI Message Data System software initializes this register by writing to it. The LSISAS1068 sends an interrupt message by writing a Dword to the address held in the Address and MSI Message Upper Address register forms bits [15:0] of the Dword message that the PCI function passes to the host. The PCI function drives bits [31:16] of this message to 0x0000 ...

Page 94

... Register: 0xXX MSI-X Message Control Read/Write 4-24 PCI Host Register Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. MSI-X Capability MSI-X Capability ID This register indicates the type of the current data structure. This register always returns 0x11, indicating MSI-X. ...

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... Table 4.3 PCI Configuration Space Register Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Function Mask Setting this bit masks all of the reset vectors that are associated with the function. This bit overrides the per- vector mask bit settings. Clearing this bit enables the per- vector mask bit to determine if a vector is masked ...

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... Register: 0xXX PCI-X Capability ID Read Only 7 0 4-26 PCI Host Register Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved MSI-X PBA Offset MSI-X PBA Offset This field contains an offset from one of the base address registers of the device that points to the MSI-X PBA. The lower 3 bits of this register are cleared (‘ ...

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... LSISAS1068 can have outstanding at one time. The LSISAS1068 uses the most recent value of this register each time it prepares a new sequence. Note that if the LSISAS1068 prepares a sequence before the setting of this field changes, the PCI function initiates the prepared sequence with the previous setting. ...

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... Data Parity Error Recovery Enable The host device driver sets this bit to allow the LSISAS1068 to attempt to recover from data parity errors. If the user clears this bit and the LSISAS1068 is operating in the PCI-X mode, the LSISAS1068 asserts SERR/ whenever the Master Data Parity Error bit in the ...

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... Reserved This field is reserved. Received Split Completion Error Message The LSISAS1068 sets this bit upon receipt of a split completion message if the split completion error attribute bit is set. Write a one (1) to this bit to clear it. Designed Maximum Cumulative Read Size These read only bits indicate a number greater than or ...

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... Requester ID and Completer ID. This field is read for diagnostic purposes only. Device Number These read only bits indicate the device number of the LSISAS1068. The PCI function uses this number as part of its Requester ID and Completer ID. This field is read for diagnostic purposes only. 20 ...

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... High Priority Request MFA Queue Reserved PCI I/O Space and Memory Space Register Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Function Number These read only bits indicate the number in the Function Number field (AD[10:8 Type 0 PCI configuration transaction. The PCI function uses this number as part of its Requester ID and Completer ID. This fi ...

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... IOP processor and vice-versa. When a host system PCI master writes to the Host Registers->Doorbell register, the LSISAS1068 generates a maskable interrupt to the IOP. The value written by the host system is available for the IOP to read in the 4-32 PCI Host Register Description Copyright © ...

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... Conversely, when the IOP processor writes to the System Interface Registers->Doorbell register, the LSISAS1068 generates a maskable interrupt to the PCI system. The host system can read the value written by the IOP in the Host Registers->Doorbell register. The host system clears the interrupt status bit and interrupt pin by writing any value to the Host Registers-> ...

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... IOP ARM processor in a reset state. The LSISAS1068 maintains this state until the PCI host clears both the Flash Bad Signature and DisARM bits. Reset History The LSISAS1068 sets this bit if it experiences a Power On Reset (POR), PCI Reset, or TestReset ...

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... Use this bit for test purposes only. Reset Adapter Setting this write only bit causes a hard reset within the LSISAS1068. The bit self-clears after eight PCI clock periods. After deasserting this bit, the IOP ARM processor executes from its default reset vector. ...

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... This register reads or writes Dword locations on the LSISAS1068 internal bus. This register is only accessible through PCI I/O Space and returns 0xFFFFFFFF if read through PCI Memory Space. The host can enable write access to this register by writing the correct Write I/O Key to the ...

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... Reserved This field is reserved. System Doorbell Interrupt The LSISAS1068 sets this bit when the IOP writes a value to the System Doorbell. The host can clear this bit by writing any value to this register. The LSISAS1068 generates a PCI interrupt when this bit is set and the corresponding mask bit in the register is cleared ...

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... This field is reserved. Interrupt Request Routing Mode This field routes PCI interrupts to the INTA/ or ALT_INTA/ pins according to the bit encodings in host system enables MSI or MSI-X, the LSISAS1068 does not signal PCI interrupts on the INTA/ or ALT_INTA/ pins. Interrupt Signal Routing Bits [9:8] Encodings ...

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... The Reply Queue provides Reply Post MFAs to the host system on reads and accepts Reply Free MFAs from the host system on writes. PCI I/O Space and Memory Space Register Description Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved Request Queue ...

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... The High Priority Request Queue accepts High Priority Request Post MFAs from the host on writes. The High Priority Request Post Queue is similar to the Request Post Queue, except that the LSISAS1068 processes requests from the High Priority Request Post FIFO before processing requests from the Request Post Queue. ...

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... Section 5.5, “Package Drawings” Please refer to the PCI Local Bus Specification, the PCI-X Addendum to the PCI Local Bus Specification, and the Serial Attached SCSI Standard for timing information. The LSISAS1068 timings conform to the information that these specifications provide. 5.1 ...

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... These numbers are specified for the design of the I/O power network. Not all of the I to the LSISAS1068 dissipates on-chip. 4. LSI Logic recommends using a heat sink for the LSISAS1068. See the LSISAS1068 Design Con- siderations SEN for more detail. 5-2 Specifications Copyright © ...

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... SATA - 3.0 Gbit/s 112 1. For more information concerning the SAS/SATA GigaBlaze transceivers, refer to the Serial Attached SCSI standard, version 1.0. DC Characteristics Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Min V Max V p-p p-p Inside EYE Outside EYE 1050 ...

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... Table 5.8 Parameter Table 5.9 Parameter I pull-up 5-4 Specifications Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. PCI-X Input Signals—CLK, RST/, GNT/, IDSEL, ALT_GNT/, CPCI64_EN/ Min V -0 0.5 VDDIO ih I -10 in PCI-X Output Signals—REQ/, INTA/, ALT_INTA/ ...

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... I - pull-down Table 5.13 10 mA, 3-State Outputs—CPCI_LED/, HB_LED/ Parameter Min V – 2 - Characteristics Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Max 0.8 VDD + 0.3 10 350 Nom Max 1.6 2 1.2 – 0.4 – – 10 105 200 Nom Max 1 ...

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... Table 5.14 Parameter Table 5.15 Parameter Table 5.16 Parameter Table 5.17 Parameter 5-6 Specifications Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. 5 mA, 3-State Outputs—TDO, TDO_ICE, RTCK_ICE, SIO_CLK_A, SIO_CLK_B, SIO_DOUT_A, SIO_DOUT_B, SIO_END_A, SIO_END_B Min V – 2 - Outputs—MCLK, ADSC/, ADV/, BWE[3:0]/, ...

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... Bidirectional Signals—SERIAL_CLK, SERIAL_DATA, ISTWI_CLK, ISTWI_DATA, GPIO[3:0], FAULT_LED[7:0]/, ACTIVE_LED[7:0]/ Parameter Min V VSS - 0 – 2 - pull-up DC Characteristics Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Max Unit 0.8 V VDD + 0.3 V 0.4 V – 350 A Max Unit 0.8 V VDD + 0.3 V 0.4 V – ...

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... Table 5.21 Parameter V in_cm V in_diff_pp V Table 5. Capacitance values do not include package capacitance. 5-8 Specifications Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. PECL Buffer Signals—REFCLK_P, REFCLK_N Min Nominal 1.6 0.6 V 0 Capacitance Capacitance (PCI-X pads) io Max 2 ...

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... For frequencies above 33 MHz, the clock frequency can not be changed beyond the spread spectrum limits except while RST/ is asserted. 2. Duty cycle not to exceed 60/40. Figure 5.1 CLK, SCLK 1 Characteristics Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Table 5.23 133 MHz 66 MHz PCI-X PCI-X Min ...

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... Figure 5.3 IRQ/ CLK 5-10 Specifications Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Table 5.24 Reset Input t 1 and Figure 5.3 provide Interrupt Output timing data. Interrupt Output Parameter CLK HIGH to IRQ/ LOW CLK HIGH to IRQ/ HIGH ...

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... External Memory Timing Diagrams This section provides timing information and examples for the external memory options available for use with the LSISAS1068. Table 5.26 Flash Write Timing Parameters Symbol Parameter t Flash Address Setup to FLASH_CS/ (Write Flash Address Setup to BWE/ (Write Enables) ...

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... NVRAM_CS/ Width (Read NVRAM Read Recover (back-to-back access) 3 – NVRAM Read Cycle Time Figure 5.6 NV Read MA A(00) MD[31:24 NVRAMCS/ MOE0/ BWE2/ 5-12 Specifications Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. A(01) A(10 A(01) A(10 A(11) A=4(00 Min ...

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... NVRAM_CS/ Width (Write NVRAM Write Recover 7 – NVRAM Write Cycle Time Figure 5.7 NV Write MA A(00) MD[31:24 NVRAMCS BWE2/ MOE/ External Memory Timing Diagrams Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. A(01) A(10 Min Max Unit 10 – – ...

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... AD[39] Y22 ECC2 AD[40] AC25 ECC3 1. Pad locations marked N/C are not internally connected to the LSISAS1068 silicon. Pad locations marked RESERVED are for LSI Logic factory test use only. Refer to Signals” to determine how to terminate the RESERVED pads. 5-14 Specifications Copyright © ...

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... N3 SIO_DIN_B RTRIM C14 SIO_DOUT_A 1. Pad locations marked N/C are not internally connected to the LSISAS1068 silicon. Pad locations marked RESERVED are for LSI Logic factory test use only. Refer to Signals” to determine how to terminate the RESERVED pads. Pinout Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...

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... VDDIO33 Y12 VSS VDDIO33 Y13 VSS 1. Pad locations marked N/C are not internally connected to the LSISAS1068 silicon. Pad locations marked RESERVED are for LSI Logic factory test use only. Refer to Signals” to determine how to terminate the RESERVED pads. 5-16 Specifications Copyright © ...

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... RXB_VDD5 E19 C11 VSS E20 1. Pad locations marked N/C are not internally connected to the LSISAS1068 silicon. Pad locations marked RESERVED are for LSI Logic factory test use only. Refer to Signals” to determine how to terminate the RESERVED pads. Pinout Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...

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... N6 CPCI_LED/ R16 N7 VDDIO33 R17 1. Pad locations marked N/C are not internally connected to the LSISAS1068 silicon. Pad locations marked RESERVED are for LSI Logic factory test use only. Refer to Signals” to determine how to terminate the RESERVED pads. 5-18 Specifications Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...

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... AD[29] AC19 AB5 AD[26] AC20 1. Pad locations marked N/C are not internally connected to the LSISAS1068 silicon. Pad locations marked RESERVED are for LSI Logic factory test use only. Refer to Signals” to determine how to terminate the RESERVED pads. Pinout Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...

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... Figure 5.8 LSISAS1068 636 EPBGA-T Diagram (Top View) 5-20 Specifications Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...

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... Package Drawings The LSISAS1068 uses a 636 EPBGA-T package. The package code is 5Y. Figure 5.9 Package Drawings Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. provides the package drawing. 5-21 ...

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... Figure 5.9 JZ02-000015-00 (5Y) Mechanical Drawing (Sheet Important: For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code 5Y. 5-22 Specifications Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...

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... JZ02-000015-00 (5Y) Mechanical Drawing; Bottom View (Sheet Important: For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code 5Y. Package Drawings Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...

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... Figure 5.9 JZ02-000015-00 (5Y) Mechanical Drawing; Bottom View (Sheet Important: For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code 5Y. 5-24 Specifications Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...

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... I/O Base Address Memory [0] Low Memory [0] High Memory [1] Low Memory [1] High Reserved Reserved Subsystem Vendor ID LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. A.3 provide a register summary. 1 Offset 0x00–0x01 0x02–0x03 0x04– ...

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... Table A.1 LSISAS1068 PCI Configuration Space Registers (Cont.) Register Name Subsystem ID Expansion ROM Base Address Capabilities Pointer Reserved Reserved Interrupt Line Interrupt Pin Minimum Grant Maximum Latency Power Management Capability ID Power Management Next Pointer Power Management Capabilities Power Management Control/Status Power Management Bridge Support Extensions — ...

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... Table A.1 LSISAS1068 PCI Configuration Space Registers (Cont.) Register Name MSI-X Message Control MSI-X Table Offset MSI-X PBA Offset PCI-X Capability ID PCI-X Next Pointer PCI-X Command PCI-X Status 1. The offset of the PCI extended capabilities registers can vary. Access these registers through the Next Pointer and Capability ID registers ...

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... Table A.3 LSISAS1068 PCI Memory [0] Space Registers Register Name System Doorbell Write Sequence Host Diagnostic Test Base Address Reserved Host Interrupt Status Host Interrupt Mask Reserved Request Queue Reply Queue High Priority Request MFA Queue A-4 Register Summary Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...

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... Wired for Management Baseline (for HBAs) Hot Plug PCI Specification Microsoft PC2001 and Server 2001 Requirements Microsoft Server Design Guide CIM Configuration Management model LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Revision 1.0 1.0a 1 ...

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... B-2 Reference Specifications Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...

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... ARM966E-S 1-4, 2-5, 4-34 aux_current bit 4-17 LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. B base address register 5-9 I/O 2-4, memory [0] memory [1] BIOS 2-9 ...

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... ID 4-2 MSI 4-19, 4-24 IX-2 Index Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. PCI-X 4-4 power management capacitance class code register CLK 3-4, 4-38 clock EEPROM external PCI ...

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... ESD 5-2 expansion ROM base address expansion ROM base address register expansion ROM enable bit 4-14 external Index Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. clock memory interface memory interface timing diagrams F 4-5 FAULT_LED[7:0]/ FIFO 2-4 reply free ...

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... IOP doorbell status bit 4-37 IRDY/ 3-5, 5-4 ISTW_CLK 3-9 ISTW_DATA 3-9 ISTWI_CLK 3-18 ISTWI_DATA 3-18 IX-4 Index Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. J junction temperature K key I/O 4-33, 4-34, L latch-up current 5-2 latency timer 4-8 latency timer register M MAD[10] ...

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... MWE[1:0]/ 3-9 N narrow port 2-18 NC 3-1 new capabilities bit 4-7 no connect 3-1 Index Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. NVSRAM NVSRAM or SRAM select NVSRAM/SRAM installed NVSRAM_CS/ O 2-17 operating conditions operating free air temperature P package drawing PAR 3-4, ...

Page 146

... IX-6 Index Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. memory write block command 2-13, 2-14 memory write command 2-11, 2-15, new capabilities bit 2-15 power management ...

Page 147

... PROCMON 3-12, 5-6 PSBRAM_CS/ 3-9 pull-ups and pull-downs 3-18 Index Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. Q queue message 4-20 reply 4-39 reply message request request message R RAID 1-1, zero channel ...

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... IX-8 Index Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. request post FIFO 2-4, request post MFA request queue register requester ID 4-30, reset adapter bit reset history bit 4-32 ...

Page 149

... TCK_ICE 3-12 TDI 3-12 TDI_ICE 3-12 TDIODE_P 3-12 TDIODE_VSS 3-12 TDO 3-12 TDO_ICE 3-12 Index Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. TMS 3-12 TMS_ICE 3-12 TN/ 3-12 TRDY/ 3-5 TRST/ 3-12 TRST_ICE/ 3-12 TST_RST/ 3-11 TX[7:0]- 3-7 ...

Page 150

... TST_RST/ 3-11, 3-18, 5-5 TTL interrupt bit 4-35 TX[3:0] 5-3 TX[7:0]- 3-7 TX[7:0]+ 3-7 IX-10 Index Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. U Ultra320 SCSI functional description 2-17 unexpected split completion bit V VDD_IO 5-2 VDDC 5-2 vendor ID register ...

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... Please include your name, phone number, fax number, and company address so that we may contact you directly for clarification or additional information. Thank you for your help in improving the quality of our documents. LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved. ...

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... Reader’s Comments Fax your comments to: Please tell us how you rate this document: LSISAS1068 PCI-X to 8-Port Serial Attached SCSI/SATA Controller, Version 2.1. Place a check mark in the appropriate blank for each category. Completeness of information Clarity of information Ease of finding information Technical content Usefulness of examples and ...

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