LSI53CF92A LSI, LSI53CF92A Datasheet
LSI53CF92A
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LSI53CF92A Summary of contents
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... TECHNICAL MANUAL LSI53CF92A Fast SCSI Controller Version 2.1 ® ...
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... Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic officer is prohibited. Document DB14-000094-02, Third Edition (April 2002) This document describes the LSI Logic LSI53CF92A Fast SCSI Controller and will remain the official reference source for all revisions of this product until rescinded by an update. ...
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... Preface This book is the primary reference and technical manual for the LSI53CF92A Fast SCSI Controller. It contains a complete functional description and includes complete physical and electrical specifications. Audience This document assumes that you have some familiarity with current and proposed SCSI standards. The people who benefit from this book are: ...
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... SCSI SCRIPTS™ Processors Programming Guide, Order No. S14044.A SCAM specification X3T9.2/93-109r5 PCI Special Interest Group 2575 N. E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344 iv Preface Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. ...
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... First version. 1.1 4/99 Miscellaneous edits, reformat. 2.0 11/00 All product names changed from SYM 2.1 12/01 Updated Tables 6.7, 6.13, and 6.15 and Figures 6.9, 6.12, and 6.16. Preface Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. ® to LSI. v ...
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... Preface Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. ...
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... SCSI Data Transfer Rates 2.6.1 2.6.2 2.7 Chip Reset LSI53CF92A Fast SCSI Controller Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. ® Technology Bus-Initiated Selection Bus-Initiated Reselection Bus-Initiated Reset Stacked Commands Mode Description Multiplexed Bus Configuration Mode Nonmultiplexed Bus Confi ...
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... Initiator Command Group 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 viii Contents Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Hard Reset Soft Reset Disconnect Reset SCSI Low-Level Programming SCAM Operations Stacked Commands No-Operation (NOP) Flush FIFO Reset Chip ...
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... Package Drawings Appendix A Register Map Appendix B Wiring Diagram Index Customer Feedback Contents Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Send Message Send Status Send Data Disconnect Sequence Terminate Sequence Target Command Complete Sequence Disconnect Receive Message Receive Command ...
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... Contents Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. ...
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... DMA Burst Mode (Nonmultiplexed Mode Reads) 2.4 SCAM Transfer Cycles 3.1 Functional Signal Grouping 3.2 LSI53CF92A 64-Pin Plastic QFP and Thin QFP Pin Configuration 4.1 REQ/ ACK/ Deassertion Delay 6.1 Rise and Fall Time Test Conditions 6.2 SCSI Input Filtering 6 ...
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... Target and Initiator Synchronous Input 6.27 64-Pin Plastic Quad Flat Pack 6.28 64-Pin Thin Quad Flat Pack B.1 Single-Pin, SE SCSI Bus Interface Wiring Diagram xii Contents Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. 6-24 6-25 6-26 6-27 6-27 6-29 6-30 B-1 ...
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... Target Command Complete Sequence 5.16 Target Receive Command Sequence 6.1 Absolute Maximum Stress Ratings 6.2 Recommended Operating Conditions 6.3 Inputs 6.4 Outputs Contents Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. 2-7 2-15 3-2 3-4 3-5 3-5 4-2 4-3 4-19 4-20 4-22 ...
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... Target Asynchronous Send Timings 6.21 Target Asynchronous Receive Timings 6.22 SCSI-1 SE Transfers (5 Mbytes/s) 6.23 Fast SCSI-2 SE Transfers (10 Mbytes/s) A.1 Register Map xiv Contents Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. 6-3 6-4 6-7 6-8 6-8 6-9 6-10 6-12 6-14 6-16 ...
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... The LSI53CF92A operates at sustained data transfer rates Mbytes/s in synchronous mode and 5 Mbytes/s in asynchronous mode. The LSI53CF92A has on-chip 48 mA drivers for Single-Ended (SE) transmission and is offered in a 64-pin Plastic Quad Flat Pack (PQFP 64-pin Thin Quad Flat Pack (TQFP) package. ...
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... SCSI-Configured AutoMatically (SCAM) Capability The LSI53CF92A differs from other members of the 53Cx9x family in that SCAM capability has been incorporated into the device. SCAM requires the ability to manipulate the SCSI control and data lines individually. To provide this capability, a low-level SCSI programming mode has been added along with hardware assist for some SCAM operations ...
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... Features Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Active negation pad cells on the SCSI Data, Parity, REQ/, and ACK/ pins to improve Fast SCSI-2 performance Input signal conditioning on the REQ/ and ACK/ lines LSI53CF92A: 64-pin PQFP or TQFP 1-3 ...
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... A1 A0 DBWR/ MODE RESET INT/ CLK 1-4 Introduction Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. illustrates the functional block diagram for the LSI53CF92A. FIFO (16 x 9-Bit) Parity Generator and Checker Steering Logic 24-Bit Transfer Counter Status Register Sequencer ...
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... Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. DREQ DACK/ DBWR/ DBRD DB[7:0] DBP 8-Bit LSI53CF92A Data Bus with Parity PAD[7:0] ALE RD/ WR/ MODE CS/ DREQ DACK/ DBWR/ DB[7:0] DBP 8-Bit LSI53CF92A Data Bus with Parity PAD[7:0] A[3:0] RD/ WR/ MODE CS 1-5 ...
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... Introduction Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. ...
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... The FSC waits for bus free, arbitrates for the bus until it acquires it, sends the message bytes followed by the CDB, then generates an interrupt. Meanwhile, a multitasking host may continue with other tasks. LSI53CF92A Fast SCSI Controller Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. 2-1 ...
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... The LSI53CF92A is the newest member of the LSI53C90 family, with additional features such as Fast SCSI transfer rates, single-pin SE SCSI, 8-bit DMA mode, and TolerANT Active Negation Technology. 2.1 Typical SCSI Operation In target mode, the microprocessor enables selection and then waits for an interrupt. Eventually an initiator selects the FSC. It then automatically steps through the selection and command phases before generating an interrupt ...
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... FIFO, these bytes are lost any command written to the Command or reselection command has to examine the bits in the Bus-Initiated Sequences Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. register. The interrupt handler that services a selection Interrupt register 2-3 ...
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... FSC to interrupt and stop. The Sequence Step register can then be examined to determine what events have been completed. 2-4 Functional Description Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Configuration 3 (Config 3) register ...
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... Identify message The bus ID is always present and is always one byte unencoded version of the state of the bus during Reselection phase. The identify message is always present and is always one byte. Bus-Initiated Sequences Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. 2-5 ...
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... In Initiator role, detected parity errors set the Parity Error bit and, if receiving SCSI bytes, assert ATN/ (Attention) prior to releasing 2-6 Functional Description Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. The settings of the SCSI-2 or Queue Tag Enable bits do not affect this operation. Configuration 1 (Config 1) ...
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... For additional information on the parity bits, refer to The LSI53CF92A has one parity pin (DBP). In both the Multiplexed Bus Configuration mode and in the Nonmultiplexed Bus Configuration mode, the processor connects to the FIFO on an 8-bit bus only. In both of these modes, the internal parity generator creates parity to send to the SCSI bus ...
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... DMA read data. A1 and A0 must be tied to ground. 2-8 Functional Description Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Dual bus; 8-bit DMA bus and 8-bit multiplexed processor address/data bus. for the setting of either mode. The two Chapter 1, “ ...
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... This is typical of a DMA interface that is slower than the SCSI device to which the system is connected. DMA Operation Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Figure 2.1 illustrates the case 2-9 ...
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... Transfer Counter drops below eight bytes and the threshold drops to one transfer. 2-10 Functional Description Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Normal DMA Mode Configuration 3 (Config 3) register in Chapter 4, “Registers.” ...
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... DREQ and assertion of DACK/ for DMA reads and writes. DMA Operation Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. The FIFO contains at least eight bytes of data to transfer to memory least the top eight bytes of the FIFO are empty to receive the eight-byte transfer from memory. Confi ...
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... When DMA Burst mode is enabled, the method by which DMA read data is transferred to the system bus depends on the bus configuration mode. The DMA read data is enabled onto the DB bus by DACK/ and either the RD/ or DBRD/ input signal, as follows. 2-12 Functional Description Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. ...
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... Figure 2.3 Figure 2.3 DREQ DACK/ 2.5.5 Single-Pin, SE SCSI The LSI53CF92A improves fast, SE SCSI performance by reducing capacitance of the SCSI input and output signals. Single pin SCSI provides the best performance for fast, SE SCSI, and reduces signal attenuation at SCSI-1 transfer rates. DMA Operation Copyright © ...
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... Sustained synchronous transfer rates of 10 Mbytes/s are attainable across the commercial voltage and temperature range. The LSI53CF92A can transfer synchronous SCSI data in both initiator and target modes at transfer rates Mbytes/s, using an input clock frequency of 40 MHz. The SCSI-1 and Fast SCSI-2 minimum ...
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... The Reset Chip command remains at the top of the Command state until a NOP command is issued. At power up, the RESET pin must be asserted as V Chip Reset Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Minimum Timing Requirements Setup 55 ns 100 ns ...
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... A SCSI reset interrupt is generated if the interrupt is not disabled by Bit 6 of the Configuration 1 (Config 1) 2-16 Functional Description Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. for further description of this command. register. If the SCSI bus reset is still active register. ...
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... LSI53CF92A SCSI protocol chip. The SCAM terminology and functionality presented within this section is consistent with definitions provided within the SCAM specification X3T9.2/93-109r5. The SCAM additions to the LSI53CF92A allow the chip Level 1 or Level 2 SCAM Master or Slave device. To provide SCAM functionality, SCSI interface chips must be able to control individual SCSI control and data lines and be able to disable active negation of signals ...
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... SCSI Low-Level Programming The LSI53CF92A design provides SCAM capability with a generic low-level SCSI programming mode. Low-level access to the SCSI bus is controlled by the Low Level bit, bit 0. When the Low Level bit is set, all SCSI bus sequences are performed using software control. Arbitration may be performed purely in software or by using the ARB bit, bit 1 ...
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... Step 3. Maintain SEL/ and MSG/ asserted with BSY/ released for a Note: Step 4. Wait until MSG/ has been released by all other devices SCAM Capabilities Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. status bit (SCAM, no ID). Examine the bus (read SCSI Bus Data Lines ...
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... Step 3. In the Step 4. In the Step 5. Release MSG/. 2-20 Functional Description Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. SCSI Output Data Latch (SODL) time, if the device is a SCAM master, C/D should also be asserted. Data Latch (SODL) register, then enabling their drivers with ...
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... When this bit is cleared, the FSC responds to normal selection attempts as soon as it detects that it is being selected (within a SCAM-tolerant selection response time). SCAM Capabilities Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. (examine the SCSI Bus Control Lines (SBCL) wired-OR glitch filtering in software. ...
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... Step 8. Release DB6. Step 9. Wait until DB6 is released by all other devices, using wired-OR 2-22 Functional Description Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. SCSI Output Data Latch (SODL) on DB[4:0], if the device is sending data, and assert DB5. Use bit 2 of the SCSI Control (SCONTROL) data onto the SCSI bus ...
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... Assert Data Bus (ADB) bit is set, the FSC generates parity for the SCSI bus using the Low Level Parity Control (LPC) bit to select even or odd parity. SCAM Capabilities Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. illustrates the SCAM Transfer Cycles. SCAM Transfer Cycles 1 ...
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... Functional Description Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. ...
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... Configuration VSS Note Multiplexed mode, these two pins must be tied to VSS. See the signal description on page 3-2 for details. LSI53CF92A Fast SCSI Controller Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. is the Functional Signal Grouping and LSI53CF92A SEL/ BSY/ ...
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... CS/ 47 RD/ 46 3-2 Signal Descriptions Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the Microprocessor and DMA Interface Signals group. Type Description B Bidirectional, active HIGH processor address-data bus with internal 200 A pull-ups. These pins allow the processor to access the internal registers of the chip at the same time the DMA bus is active ...
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... DREQ 2 DACK/ 3 CLK 48 RESET 44 Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Type Description I Active LOW register write signal. This TTL- compatible input causes the FSC to write data into its internal registers when CS/ is also true. O Active LOW, open drain interrupt signal to the microprocessor ...
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... CD/, 37 IO/ 39 3-4 Signal Descriptions Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the SCSI Signals group. Type Description B 48 mA, SCSI data/parity output bus. These pins are active LOW SCSI data signals. These signals are actively deasserted when Active Negation is enabled and the chip is active on the SCSI bus ...
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... HIGH. I Test In. When this pin is driven LOW, the LSI53CF92A connects all inputs and outputs to an “AND” tree. The SCSI control signals and data lines are not connected to the “AND” tree. The output of the “AND” tree is connected to the DREQ pin. This ...
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... DACK/ DBWR/ VDD DB0 DB1 DB2 VSS DB3 DB4 DB5 VSS DB6 DB7 DBP 1. See 3-6 Signal Descriptions Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. LSI53CF92A 64-Pin Plastic QFP and Thin QFP Pin 1 Configuration LSI53CF92A 64-Pin PQFP/TQFP ...
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... Flags, and This chapter contains the following sections: Section 4.1, “Standard Register Set” Section 4.2, “SCAM Register Set” LSI53CF92A Fast SCSI Controller Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. All register values are given in Transfer Counter registers ...
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... Reserved bits should be masked when read. All register bits in the LSI53CF92A are cleared to zero after a hard reset, except as noted in Table 4.1. The shaded area in Table 4.1 Register Transfer Count Transfer Counter High/ID Register Destination Bus ID Status Clock Conversion Factor Synchronous Transfer Period ...
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... Configuration 3 (Config 3) 0x0D Configuration 4 (Config 4) 0x0E Transfer Counter High/ID 0x0F Reserved Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Configuration Register 4, Bit Register Bank 0 Register Bank 1 Write Read Low Transfer Counter Transfer Counter Low ...
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... Mbytes. These registers are not changed by any reset. Their states are unpredictable after power-up. 4-4 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Configuration 4 (Config 4) selects between two banks of Table 4.2 ...
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... Initiator Decremented by – Message In, Status ACK/ – Message Out, Command DACK DMA Burst mode, the transfer counter decrements on the leading edge of RD/, DBRD/, DBWR/, and DACK/ as follows: Standard Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved Default ...
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... Descriptor Block (CDB), loads the counter with the number of bytes in the CDB, then decrements once for every byte received. 4-6 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Data In phase DMA Write, Multiplex Bus Mode DBWR/ DMA Write, Nonmultiplex Bus Mode DACK/ ...
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... FIFO are not changed by any reset but when the flags are zero, successive FIFO reads access the bottom register. This register changes during any DMA or SCSI bus activity. The default value of this register is 0x00. Standard Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved Default ...
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... SCSI bus disconnect Bus-initiated selection or reselection Select command Reconnect command if ATN/ is set Select or Reselect time-out Target Terminate command Parity error detected in target mode Assertion of ATN/ in target mode 4-8 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. 6 Command Code (CC) Default ...
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... FIFO. Otherwise, an illegal command interrupt is generated. For example, after a hardware or software reset, the FSC is in the Standard Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Interrupt register, and Interrupt register change to ...
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... They may be latched (for stacked commands) by setting INT 4-10 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. disconnected state. A command from either the target group or the initiator group causes an Illegal Command interrupt. An Enable Selection/Reselection command by itself does not change modes. However, if another SCSI device then selects the FSC the target state ...
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... Reading the Interrupt register does not clear this bit. Hardware reset or the Reset Chip command clears it, but SCSI reset does not. Standard Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Command register has been register and the FSC detects ...
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... VOC MSG, C/D, I/O 4-12 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Valid Group Code When the FSC is selected, this bit decodes the group code field in the first byte of the Command Descriptor Block (CDB). If the group code matches one defined in ANSI X3 ...
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... SCSI bus. The most significant five bits are reserved. The destination ID is not changed by any reset; the states of these bits are unpredictable after power-up. Standard Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. register. The transparent latch SCSI Bus Phase Data Out ...
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... The entire Interrupt register is cleared (0x00 hardware reset or the Reset command, but not SCSI reset. The default value of this register is 0x00. Note: SRST ILCMD DIS 4-14 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved ILCMD DIS BS Default 0 ...
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... Standard Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. No selection interrupt Selected without ATN/; FSC has been selected as a Target with ATN/ false Selected with ATN/; FSC has been selected as a Target with ATN/ true SCAM selection. FSC has detected a SCAM ...
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... The unchanged by any reset, and the states of these bits are unpredictable after power-up. 4-16 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved Default ...
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... The sequence step counter is set to zero at the beginning of certain commands. The counter is then incremented at specific points in the various algorithms to aid in error recovery. The possible states are described in Chapter 5, “Command Set.” Standard Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved SOM SS[2:0] ...
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... REQ/ (Request) or ACK/ (Acknowledge) pulses. Synchronous data is transmitted or received at the rate of one byte every “n” Clocks (CLK). The variable “n” is related to the register value and the data transfer rate as shown in 4-18 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved Default ...
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... Standard Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Clocks Transfer Rate per Byte (Mbytes/s) 4 10.0 5 8.0 6 6.6 7 5.7 8 5.0 9 4.4 10 4.0 11 3.6 12 3 ...
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... The upper three bits are reserved by LSI Logic. This register defaults to 0x55 after hardware reset or the Reset Chip command (but not SCSI reset). Refer to the descriptions for the FASTCLK and FASTSCSI bits, Configuration 3 (Config operation. Note: 4-20 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. ...
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... Synchronous Data In or Synchronous Data Out phase. The control over deassertion of these signals is measured in input clock cycles and is dependent on the status of the FASTCLK bit, bit 3, as shown in Table 4.5. Standard Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved FF4 FF3 FF2 ...
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... REQ/ or ACK/), depending on whether the FSC is in initiator or target mode. 4-22 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. REQ/ ACK/ Deassertion Delay Selection Synchronous REQ/ ACK/ Offset Register ...
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... CLK REQ/ ACK/ SYNC Offset Register Value (Bits [5:4]) FASTCLK Disabled Note: The input clock duty cycle affects the half clock assertion/deassertion delays. Standard Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved (Bits [7:6 (Bits [7:6]) 4-23 ...
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... This 8-bit read/write register specifies various operating conditions for the FSC. Any bit pattern written to this register may be read back and should be identical. The default value of this register is 0x00. Slow SRD PTest 4-24 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved SRD PTest PChk CTEST ...
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... This three-bit field is binary encoded reset by hard reset but not by SCSI reset; after power-up the states of these bits are unpredictable. Standard Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Status register but does Status register is not set, and ATN/ is not Section 2.3, “ ...
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... These bits must never be loaded with a binary 0b001. Hardware Reset or the Reset command sets the Clock Conversion Factor to a binary 0b010. The upper five bits of this register are reserved. 4-26 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. R Default x x ...
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... Any target command is accepted by the FSC. For example, a DMA command loads or unloads the FIFO and sets the SCSI phase, Data, and REQ/ signals even if arbitration and selection have not occurred. Standard Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved HIGH-Z ...
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... LSI53C90 family software. Any bit pattern written to this register may be read back and should be identical. The default value of this register is 0x20 DHZ 4-28 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved DHZ SCSI2 Default ...
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... Group 2 commands as reserved commands, it requests only six bytes in Command phase, and does not set the Valid Group Code status bit. Standard Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Transfer Counter register description. register. Section 2.2, “Bus-Initiated ...
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... IMRC 0 After a hardware reset or a software Chip Reset, the bits in this register are all cleared, which makes the chip compatible with LSI53C90 family software. Any bit pattern written to this register may be read back and should be identical, except that bit 2 remains low. ...
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... ATN/ true. If the validation check fails, the selection sequence halts and the chip generates an interrupt. QTE Queue Tag Enable When this bit is set, the LSI53CF92A can receive 3-byte messages during bus-initiated Select With ATN. A similar feature is also enabled by setting bit 3 in the Configuration 2 (Config 2) consist of a one-byte identify message and a two-byte queue tag message ...
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... FCLK R ADMA 4-32 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. FASTCLK Along with bit 4, this bit informs the device that it is connected to a fast clock, and to select between Fast SCSI timings and SCSI-1 timings. Fast SCSI operation requires a 40 MHz clock. A fast clock is one with a frequency greater than 25 MHz ...
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... Alternate DMA mode. When Threshold Eight is set, the maximum synchronous offset is limited to seven. DREQ goes true during DMA reads and writes as follows. Standard Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. 2.2 and 0 4-33 ...
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... SCSI reset. Note 4-34 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. DMA Write to FIFO DREQ is true whenever the top eight bytes of the FIFO are empty. DMA Read from FIFO End of transfer Target mode: DREQ is set when the transfer counter is zero or ATN/ is set ...
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... Reading this register can also provide the chip revision code when the following conditions are met: A hard reset has occurred; and The register has not been loaded with a transfer count. Standard Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. ® Technology,” ...
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... To provide register structures for directly controlling and observing SCSI bus activity thus providing SCAM functionality, an additional addressing mode was created for the LSI53CF92A to allow access to the new registers. This is because the original address map for the LSI53CF92A was limited to 16 registers and only two read only addresses were available ...
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... FSC ignores the selection attempt. This functionality allows a SCAM Master to scan the SCSI bus for SCAM tolerant (“old”) devices using short selection time-outs. Unassigned SCAM slaves do SCAM Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved ...
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... ADB ARB LL 4-38 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. not respond to this initial bus scan because of their delayed response. After a SCAM slave has been assigned an ID, this bit should be cleared to enable normal selection response. Enable SCAM Selection Response When this bit is set, the FSC monitors the SCSI bus for SCAM selections ...
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... SCSI bus. ARB1 Arbitration Delay1 This bit is set when one arbitration delay has passed since the FSC detected bus-free and started arbitrating for the SCSI bus. SCAM Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved SDP SRST ARB4 ...
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... RESET pin, a SCSI Bus reset, chip power-up, and held reset whenever the Low Level mode bit is cleared. REQ ACK BSY SEL ATN MSG C/D I/O 4-40 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved ACK BSY SEL Default (Bit set = assert SCSI REQ/) ...
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... ATN (Bit Set = SCSI ATN/ Asserted) MSG (Bit Set = SCSI MSG/ Asserted) C/D (Bit Set = SCSI C/D/ Asserted) I/O (Bit Set = SCSI I/O/ Asserted) SCAM Register Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved SEL ATN MSG Default 0 ...
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... SCSI Bus Data Lines (SBDL) Read Only Register Bank 1 7 SD7 x SD[7:0] 4-42 Registers Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. SD6 SD5 SD4 Default (Bit Set = Assert SCSI Data Bit) This register provides low-level control of the SCSI bus data signals ...
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... Chapter 5 Command Set All LSI53CF92A instructions may be issued in two forms: DMA and non-DMA. DMA commands move data between memory and the SCSI bus, while non-DMA commands move data between the FIFO and the SCSI bus. Non-DMA commands require the microprocessor to move data between the FIFO and memory ...
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... Command Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Miscellaneous Group NOP Flush FIFO Reset Chip Reset SCSI Bus Disable Selection/Reselection Disconnected State Group Reselect Sequence Select without ATN Sequence Select with ATN Sequence ...
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... Command stacking should only be used during Data In and Data Out phase. If stacking is used in initiator mode recommended that the Features Enable bit in SCSI phase lines to be latched at the end of a command. Illegal Commands Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Target Group Disconnect Receive Message Receive Command ...
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... This command resets all functions in the chip and returns disconnected state. The command has the same effect as a hardware reset. 5-4 Command Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the Miscellaneous commands. Miscellaneous Commands DMA Mnemonic ...
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... Function Complete Interrupt bit is not set inadvertently if the selection or reselection sequence continues after this command has been loaded. Miscellaneous Command Group Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Chapter 4, “Registers.” For CCF = 0, indicating 8 clocks, on page 2-4, ...
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... The sequence terminates early if a Reselect time-out occurs terminates normally, a Function Complete interrupt occurs. 5-6 Command Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. register is cleared, and the FSC generates an illegal lists the Disconnected State commands. Disconnected State Commands ...
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... ATN/ true until the FIFO empties DMA Transfer Information command is used, ATN/ remains true until the transfer counter decrements to zero. Disconnected State Command Group Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. registers must have been programmed previously. and Destination Bus ID ...
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... Command Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the Target Selected without ATN sequence. Interpretation Selected, loaded bus ID into FIFO, loaded null-byte message into FIFO. Stopped in Command phase due to parity error; some command descriptor block bytes may not have been received ...
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... Disconnected State Command Group Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the Target Selected with ATN Sequence, SCSI-2 Bit or Interpretation Selected with ATN/, stored bus ID and one message byte; stopped due to either parity error or invalid ID message. Initiator released ATN/ after one message byte received. ...
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... Command Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the Initiator Select without ATN sequence. Interpretation Arbitration complete; selection time-out; disconnected. Arbitration and selection complete; stopped because target did not assert command phase. Stopped during command transfer because target prematurely changed phase ...
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... Command phase early completes normally, a Function Complete and Bus Service interrupt are generated. Disconnected State Command Group Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the Initiator Select with ATN and Stop sequence. Interpretation Arbitration complete; selection time-out; disconnected. ...
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... The interrupt output occurs 1.5 to 3.5 CLK cycles after BSY/ goes false. 5-12 Command Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the Initiator Select with ATN3 sequence. Interpretation Arbitration complete; selection time-out; disconnected. Arbitration and selection complete; stopped because target did not assert Message Out phase ...
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... SCSI bus parity error occurred during the Data In phase, the parity bit is not set nor is ATN/ asserted until after the FSC receives the subsequent Transfer Information command. Initiator Command Group Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Status register and ATN/ is set on the 5-13 ...
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... REQ/ for the next byte. Thus non-DMA Transfer Information commands generate an interrupt for every byte received. 5-14 Command Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the Initiator commands. Initiator Commands DMA Mnemonic ...
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... ACK/ asserted after receiving the last message byte. To accept the message, issue this command. To reject the message, set ATN/ and then issue this command. Initiator Command Group Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Command register and 5-15 ...
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... ATN/ on the last byte of a Message Out phase. The Reset ATN command is provided for older devices that do not respond properly to the ATN/ condition. 5-16 Command Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. command, except that the FSC ...
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... If the FSC was idle when ATN was asserted, a Bus Service interrupt is generated, the Function Complete bit is zero, and the Target Command Group Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Command for details. register, and generates an ...
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... This command causes the FSC to assert Data In phase and sends bytes until the FIFO is empty, or the transfer counter is zero and the FIFO is empty (if DMA). DMA must be used for synchronous transfers. 5-18 Command Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the Target commands. Target Commands DMA Mnemonic ...
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... FSC does not disconnect. If ATN/ is not asserted by the initiator, a disconnect interrupt is generated. Target Command Group Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the Target Disconnect sequence. Interpretation Sent one message byte; stopped because initiator set ATN/. ...
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... CLK frequency and the clock conversion factor). The FSC returns to the Disconnected state without generating an interrupt. 5-20 Command Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the Target Terminate sequence. Interpretation Sent one status byte; stopped because initiator set ATN/. ...
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... Group 6 vendor unique commands, 10 bytes for Group 7 vendor unique commands, and 12 bytes for Group 5 commands. Target Command Group Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Configuration 2 (Config 2) register, 5-21 ...
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... Either the Target Send Data or Target Receive Data command is operating The DMA controller has halted 5-22 Command Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the Target Receive Command sequence. Interpretation Stopped during command transfer due to parity error; check FIFO flags. ...
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... ACK/s have been received. No extra bits are set in the registers. The microprocessor receives the interrupt from the command that was in progress, and the command FIFO is cleared. Target Command Group Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. (Status register (Sequence Step ...
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... Command Set Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. ...
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... Recommended Operating Conditions not implied. LSI53CF92A Fast SCSI Controller Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. 6.1 through 6.5 describe the LSI53CF92A DC electrical Pins Min – 55 – 0.5 – ...
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... Input low voltage IL I Input leakage current IN V Hysteresis H I Input leakage current IL C Capacitance IN 6-2 Electrical Specifications Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Pins Min Max – 4.75 5.25 – – 1 – – 50 – – ...
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... Input current, low IL I Input current, high IH I HIGH-Z pull-up PU current C Capacitance IO 1. TolerANT active negation not enabled. DC Electrical Characteristics Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Pins Min DREQ 2.4 DREQ, INT RST/, SEL ACK/, REQ/, BSY/, SDP, SD[7:0] – ...
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... Single pin only; irreversible damage may occur if sustained for one second. 4. SCSI RESET pin 6-4 Electrical Specifications Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. provides electrical characteristics for SE SCSI signals. Figures 6.5 provide reference information for testing SCSI signals. ...
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... Note the input filtering period, register programmable (Bit 4 of the 1 Configuration 3 (Config 3) Figure 6 TolerANT Active Negation Technology Specifications Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Rise and Fall Time Test Conditions 2 register 0x0C to either ns. ...
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... Output Current as a Function of Output Voltage 0 200 400 600 800 Output Voltage (Volts) 6-6 Electrical Specifications Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Input Current as a Function of Input Voltage 8.2 V 0.7 V OUTPUT ACTIVE Input Voltage (Volts) 100 80 60 ...
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... DB[7:0], DBP SDP, SD[7:0], RST/, SEL/, BSY/, ATN/, MSG/, CD/, IO/, REQ/, ACK/ AC Electrical Characteristics Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. 70 ˚C. Output timing is based on simulation under worst-case A Performance numbers are based upon the FSC operating with a 40 MHz clock. Other clock inputs also allow for increased transfer rates in proportion to their frequencies ...
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... CH t Clock LOW time CL t Clock period CP t Synchronization latency = Minimum frequencies to meet ANSI timing specifications. 6-8 Electrical Specifications Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. illustrates the clock input. Table 6.8 Table 6.9 Clock Input ...
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... Table 6.10 Reset Timing Symbol Parameter t RESET pulse width RST 1. At power-up, the RESET pin must be asserted Electrical Characteristics Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. and Table 6.10 provide Reset timing data. Reset Input t RST Min Max 3 t – ...
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... Refer to the register read specifications for the timing requirements of CS/, RD/, and address for reading the Interrupt register. 6-10 Electrical Specifications Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. and Table 6.11 provide Interrupt timing data. Interrupt Output t ...
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... Figure 6.9 A[3:0] CS/ RD/ PAD[7:0] Figure 6.10 Figure 6.10 Register Write, Nonmultiplexed PAD Bus A[3:0] CS/ WR/ PAD[7:0] AC Electrical Characteristics Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. illustrates the Register Read, Nonmultiplexed PAD bus. Register Read, Nonmultiplexed PAD Bus ...
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... If DMA is active, the FIFO must not be accessed must also be satisfied WR/ is held LOW, the data setup to CS/ HIGH minimum. 13 6-12 Electrical Specifications Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the Register Interface, Nonmultiplexed PAD bus. Min – t ...
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... Figure 6.11 Register Read, Multiplexed PAD Bus ALE CS/ RD/ PAD[7:0] Figure 6.12 Figure 6.12 Register Write, Multiplexed PAD Bus ALE CS/ WR/ PAD[7:0] AC Electrical Characteristics Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. illustrates the Register Read, Multiplexed PAD bus Address illustrates the Register Write, Multiplexed PAD bus ...
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... If WR/ is held LOW, data setup to CS/ HIGH minimum for successive FIFO reads or a FIFO write/read followed by a read the FIFO Flags register. 6-14 Electrical Specifications Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the Register Interface, Multiplexed PAD bus. Min – t ...
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... DB[7:0], DBP Figure 6.14 Figure 6.14 DMA Write, Nonmultiplexed Mode Only DREQ DACK/ DBWR/ DB[7:0], DBP AC Electrical Characteristics Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. illustrates the DMA Read, Nonmultiplexed Mode only illustrates the DMA Write, Nonmultiplexed Mode only. ...
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... DBWR/ edges may precede or follow DACK/ edges. Recommended values are DBWR/ is held LOW, the data setup to DACK/ HIGH minimum; data hold from DACK/ HIGH minimum. 6-16 Electrical Specifications Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the DMA Interface, Nonmultiplexed Mode only. Min – 30 ...
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... Figure 6.15 DMA Read, Multiplexed Mode Only DREQ DACK/ DBRD/ DB[7:0], DBP Figure 6.16 Figure 6.16 DMA Write, Multiplexed Mode Only DREQ DACK/ DBWR/ DB[7:0], DBP AC Electrical Characteristics Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. illustrates the DMA Read, Multiplexed Mode only ...
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... DBWR/ trailing edge may precede or follow DACK/ trailing edge. The recommended value is DBWR/ is past DACK/, the data setup to DACK/ HIGH minimum; data hold from 14 DACK/ HIGH minimum. 6-18 Electrical Specifications Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the DMA Interface, Multiplexed Mode only. 1 Min – ...
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... DACK/ DBRD/ DB[7:0], DBP Figure 6.18 Figure 6.18 Burst Mode DMA Write, Multiplexed Mode Only DREQ DACK/ DBWR/ DB[7:0], DBP AC Electrical Characteristics Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. illustrates the Burst Mode DMA Read, Multiplexed Mode only ...
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... Assertion pending. If the FIFO is empty during DMA read, or full during DMA write, then assertion is not pending. 2. Single DMA transfer only. 3. Multiple DMA transfers only. 6-20 Electrical Specifications Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the Burst Mode DMA Interface, Multiplexed Mode. Min 30 – t ...
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... DBP Figure 6.20 Mode only. Figure 6.20 Burst Mode DMA Write, Nonmultiplexed Mode Only DREQ DACK/ DBWR/ DB[7:0], DBP AC Electrical Characteristics Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. illustrates the Burst Mode DMA Read, Nonmultiplexed illustrates the Burst Mode DMA Write, Nonmultiplexed ...
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... Either DACK/ or DBWR/ may toggle during a burst write. Timings are shown for DBWR/ toggling; however, DACK/ and DBWR/ may be interchanged in 6. DBWR/ LOW may precede DACK/ LOW. 6-22 Electrical Specifications Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. lists the Burst Mode DMA Interface, Nonmultiplexed Mode. Min 30 – ...
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... SCSI Timing Diagrams Figures LSI53CF92A SCSI timing. Figure 6.21 Initiator Asynchronous Send SD[7:0], SD0 ACK/ REQ/ Table 6.18 Initiator Asynchronous Send Timings Symbol Parameter t Data setup to ACK/ LOW 1 t ACK/ HIGH from REQ/ HIGH 2 t Data hold from REQ/ HIGH ...
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... Symbol Parameter t Data setup to REQ/ LOW 1 t ACK/ LOW from REQ/ LOW 2 t Data hold from ACK/ LOW 3 t ACK/ HIGH from REQ/ HIGH 4 6-24 Electrical Specifications Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved Min Max Unit – ...
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... Target Asynchronous Send Timings Symbol Parameter t Data setup to REQ/ LOW 1 t REQ/ HIGH from ACK/ LOW 2 t Data hold from ACK/ LOW 3 t REQ/ LOW from ACK/ HIGH 4 SCSI Timing Diagrams Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved Min Max Unit – ...
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... Symbol Parameter t REQ/ HIGH from ACK/ LOW 1 t REQ/ LOW from ACK/ HIGH 2 t Data setup to ACK/ LOW 3 t Data hold from REQ/ HIGH 4 6-26 Electrical Specifications Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved Min Max Unit – ...
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... Figure 6.25 Target and Initiator Synchronous Output SDx REQ/, ACK/ Figure 6.26 Target and Initiator Synchronous Input SDx REQ/, ACK/ SCSI Timing Diagrams Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved 6-27 ...
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... REQ/ or ACK/ assertion period 5 t REQ/ or ACK/ negation period 6 t Data setup to REQ/ LOW or ACK/ LOW 7 t Data hold from REQ/ LOW or ACK/ LOW 8 6-28 Electrical Specifications Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Min Max Unit 90 – – – ns 100 – ...
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... Package Drawings Figure 6.27 Figure 6.28 LSI53CF92A. Figure 6.27 64-Pin Plastic Quad Flat Pack Package Drawings Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. is the 64-Pin Plastic Quad Flat Pack package drawing and is the 64-Pin Thin Quad Flat Pack drawing for the 17 ...
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... Figure 6.28 64-Pin Thin Quad Flat Pack 6-30 Electrical Specifications Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. 12.0 BSC. 10.0 BSC. Pin 49 64-Pin Thin Quad Flat Pack Pin 1 0 Min 0 –7 0.20 Min 0.50 BSC. Pin 33 0.17 Min Pin 17 0 ...
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... FIFO Flags Interrupt Reserved Sequence Step Status Synchronous Offset Synchronous Transfer Period Test Time-Out Transfer Counter LSI53CF92A Fast SCSI Controller Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Chapter 4, “Registers.” Address Read/Write 0x09 Write Only 0x03 Read/Write 0x08 ...
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... SCSI Bus Data Lines (SBDL) SCSI Control (SCONTROL) SCSI Output Control Latch (SOCL) SCSI Output Data Latch (SODL) SCSI Status (SSTATUS) A-2 Register Map Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. Address Read/Write 0x00–0x01 Read Only 0x0E Read/Write ...
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... Wiring Diagram Figure B.1 Single-Pin, SE SCSI Bus Interface Wiring Diagram DMA Controller/ Microprocessor Interface + 5 V 2.2 k 10–40 MHz LSI53CF92A Fast SCSI Controller Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. LSI53CF92A DBP SDP DB7 SD7 DB6 SD6 DB5 ...
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... B-2 Wiring Diagram Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. ...
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... FIFO 5-4 NOP 5-4 reset chip 5-4 reset SCSI bus 5-5 LSI53CF92A Fast SCSI Controller Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. target command group disconnect disconnect sequence receive command receive command sequence receive data receive message ...
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... M multiplexed bus configuration mode 2-8 N nonmultiplexed bus configuration mode normal DMA mode 2-9 IX-2 Index Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. P parity checking and generation parity control R register bits clock conversion register 6-19 clock conversion bits 6-21 ...
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... Index Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. S SCAM 4-36 SCAM register set SCSI bus control lines (SBCL) register SCSI ACK/ asserted bit SCSI ATN/ asserted bit ...
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... TolerANT specifications 6-6 TolerANT technology 1-2 transfer counter high/ID register 4-35 chip family ID bits 4-36 chip revision level bits 4-36 transfer counter register 4-4, 4-5 IX-4 Index Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. ...
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... Please include your name, phone number, fax number, and company address so that we may contact you directly for clarification or additional information. Thank you for your help in improving the quality of our documents. LSI53CF92A Fast SCSI Controller Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved. ...
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... Reader’s Comments Fax your comments to: Please tell us how you rate this document: LSI53CF92A Fast SCSI Controller. Place a check mark in the appropriate blank for each category. Completeness of information Clarity of information Ease of finding information Technical content Usefulness of examples and illustrations Overall manual ...
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... You can find a current list of our U.S. distributors, international distributors, and sales offices and design resource centers on our web site at http://www.lsilogic.com/contacts/na_salesoffices.html ...
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