ICE3PCS01G Infineon Technologies, ICE3PCS01G Datasheet - Page 13

• Manufacturer Part Number: ICE3PCS01G
• Description: Power Factor Correction ICs STANDALONE PFC CTRLR IN CCM
• Manufacturer: Infineon Technologies

Specifications of ICE3PCS01G

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Figure 9
The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 4
(ICOMP). The PWM cycles starts with the Gate turn off
for a duration of T
kept discharged. The ramp is allowed to rise after the
T
ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current
and the off duty cycle D
Figure 10 shows the timing diagrams of the T
the gate waveforms.
Figure 10
3.7
The PWM logic block prioritizes the control input signal
and generates the final logic signal to turn on the driver
stage. The speed of the logic gates in this block,
together with the width of the reset pulse T
designed to meet a maximum duty cycle D
at the GATE output under 65kHz of operation.
In case of high input currents which results in Peak
Current Limitation, the GATE will be turned off
Version 2.0
Gate
Drive
Clock
V
V
GATE
OFFMIN
C,ref
ram p
(1)
(1)
V
c,ref
is a function of V
expires. The off time of the boost transistor
PWM Logic
Ramp Profile
Average Current Control in CCM
ICOMP
Ramp and PWM waveforms
OFFMIN
OFF
T
off _min
(600ns typ.) and the ramp is
.
600 ns
Ave(I
Released
Ramp
in
) at ICOMP
PWM Cycle
MAX
OFFMIN
OFFMIN
of 95%
, are
and
t
t
13
immediately and maintained in off state for the current
PWM cycle. The signal T
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 11.
Figure 11
3.8
The IC provides numerous protection features in order
to ensure the PFC system in safe operation.
3.8.1
Brownout occurs when the input voltage V
the minimum input voltage of the design (i.e. 85V for
universal input voltage range) and the V
entered into the V
BOP, the boost converter will increasingly draw a
higher current from the mains at a given output power
which may exceed the maximum design values of the
input current.
ICE3PCS01G provides a new BOP feature whereby it
senses directly the input voltage for Input Brown-Out
condition via an external resistor/capacitor/diode
network shown in Figure 12. This network provides a
filtered value of VIN which turns the IC on when the
voltage at pin 9 (BOP) is more than 1.25V. The IC
enters into the fault mode when BOP goes below 1.0V.
The hysteresis prevents the system to oscillate
between normal and fault mode. Note also that the
peak of VIN needs to be at least 20% of the rated V
in order to overcome OLP and powerup system.
Peak current limit
PWM on signal
Current loop
T
600ns
off _min
System Protection
Input Voltage Brownout Protection(BOP)
limit Latch
PWM on
Current
R
S
Latch
R
S
CCUVLO
Q
Q
Q
Q
PWM LOGIC
Functional Description
level yet. For a system without
OFFMIN
resets (highest priority,
ICE3PCS01G
CCM-PFC
5 May 2010
High = turn on Gate
IN
CC
falls below
has not
OUT