STPCI2HDYI STMicroelectronics, STPCI2HDYI Datasheet
STPCI2HDYI
Specifications of STPCI2HDYI
Related parts for STPCI2HDYI
STPCI2HDYI Summary of contents
Page 1
POWERFUL x86 PROCESSOR ■ 64-BIT SDRAM UMA CONTROLLER ■ GRAPHICS CONTROLLER - VGA & SVGA CRT CONTROLLER - 135MHz RAMDAC - ENHANCED 2D GRAPHICS ENGINE ■ VIDEO INPUT PORT ■ VIDEO PIPELINE - UP-SCALER - VIDEO COLOUR SPACE CONVERTER ...
Page 2
STPC® ATLAS DESCRIPTION The STPC Atlas integrates a standard 5th generation x86 core along with a powerful UMA graphics/video chipset, support logic including PCI, ISA, Local Bus, USB, EIDE controllers and combines them with standard I/O interfaces to provide a ...
Page 3
TFT Interface ■ Programmable panel size up to 1024 by 1024 pixels. ■ Support for VGA and SVGA active matrix TFT flat panels with 9, 12, 18-bit interface (1 pixel per clock). ■ Support for XGA and SXGA active ...
Page 4
STPC® ATLAS ■ PCMCIA interface ■ Support one PCMCIA 68-pin standard PC Card Socket. ■ Power Management support. ■ Support PCMCIA/ATA specifications. ■ Support I/O PC Card with pulse-mode interrupts. ■ USB Interface ■ USB 1.1 compatible. ■ Open HCI ...
Page 5
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7
DEBUG METHODOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 8
STPC® ATLAS 1 GENERAL DESCRIPTION At the heart of the STPC Atlas is an advanced processor block that includes a powerful x86 processor core along with a 64-bit SDRAM controller, advanced 64-bit accelerated graphics and video controller, a high speed ...
Page 9
Modem Ring Resume Detection. The STPC Atlas implements a multi-function parallel port. The standard PC/AT compatible logical address assignments for LPT1, LPT2 and LPT3 are supported. It can be configured for any of the following ...
Page 10
STPC® ATLAS Figure 1-1. Functional description. Host x86 I/F Core SDRAM CTRL 10/108 1 PCI Bus PCI m/s PMU ISA IPC m/s PCMCIA LB CTRL Video Pipeline C Key K Key LUT SVGA CRTC Cursor GE I/F VIP USB I/Os ...
Page 11
CLOCK TREE The STPC Atlas integrates many features and generates all its clocks from a single 14MHz oscillator. This results in multiple clock domains as described in Figure 1-2. Figure 1-2. STPC Atlas clock architecture VCLK VIP CRTC,Video,TFT 48MHz ...
Page 12
STPC® ATLAS Figure 1-3. Typical ISA-based Application. 5V tolerant Flash ISA ROMCS# IRQ DMA.ACK DMA.REQ PCI 12/108 1 RTC EIDE USB Boot STPC Atlas SDRAM SVGA TFT 2 Serial Ports Keyboard Parallel Port Mouse VIP 16 GPIOs ...
Page 13
Figure 1-4. Typical PCMCIA-based Application. 5V tolerant Flash PCMCIA ROMCS# PCI EIDE USB Boot STPC Atlas SDRAM STPC® ATLAS SVGA TFT 2 Serial Ports Keyboard Parallel Port Mouse VIP 16 GPIOs 13/108 1 ...
Page 14
STPC® ATLAS Figure 1-5. Typical Local-Bus-based Application. Flash Local Bus IRQ PCI 14/108 1 RTC EIDE USB Boot STPC Atlas SDRAM SVGA TFT 2 Serial Ports Keyboard Parallel Port Mouse VIP 16 GPIOs ...
Page 15
PIN DESCRIPTION 2.1. INTRODUCTION The STPC Atlas integrates functionalities of the PC architecture. Therefore, many of the traditional interconnections between the host PC microprocessor and the peripheral devices are totally internal to the STPC Atlas. This offers improved performance ...
Page 16
STPC® ATLAS Table 2-2. Definition of Signal Pins Signal Name Dir Buffer Type CS#[1:0] O BD8STRP_TC CS#[3]/MA[12]/BA[1] O BD16STARUQP_TC CS#[2]/MA[11] O BD16STARUQP_TC MA[10:0] O BD16STARUQP_TC Memory Row & Column Address BA[0] O BD16STARUQP_TC Bank Address RAS#[1:0] O BD16STARUQP_TC Row Address ...
Page 17
Table 2-2. Definition of Signal Pins Signal Name Dir Buffer Type RTCDS# O BD4STRP_FT RTCAS O BD4STRP_FT RMRTCCS# O BD4STRP_FT GPIOCS# I/O BD4STRP_FT IRQ_MUX[3:0] I BD4STRP_FT DACK_ENC[2:0] O BD4STRP_FT DREQ_MUX[1:0] I BD4STRP_FT TC O BD4STRP_FT ISAOE# I BD4STRP_FT KBCS# I/O ...
Page 18
STPC® ATLAS Table 2-2. Definition of Signal Pins Signal Name Dir Buffer Type FCS_0H# O BD8STRP_FT FCS_0L# O BD8STRP_FT FCS_1H# O BD8STRP_FT FCS_1L# O BD8STRP_FT 1 IRQ_MUX[3:0] I/O BD4STRP_FT IDE CONTROLLER DD[15:12] I/O BD4STRP_FT DD[11:0] I/O BD8STRUP_FT DA[2:0] O BD8STRUP_FT ...
Page 19
Table 2-2. Definition of Signal Pins Signal Name Dir Buffer Type USB INTERFACE OC I TLCHTU_TC 1 USBDPLS[0] I/O USBDS_2V5 1 USBDMNS[0] 1 USBDPLS[1] I/O USBDS_2V5 1 USBDMNS[1] 1 POWERON O BT4CRP SERIAL CONTROLLER CTS0#, CTS1# I TLCHT_FT DCD0#, DCD1# ...
Page 20
STPC® ATLAS Table 2-2. Definition of Signal Pins Signal Name Dir Buffer Type SPKRD O BD4STRP_FT 1 Note ; See Table 2-3 for buffer type descriptions Table 2-3. Buffer Type Descriptions Buffer ANA Analog pad buffer OSCI13B Oscillator, 13 MHz, ...
Page 21
SIGNAL DESCRIPTIONS 2.2.1. BASIC CLOCKS AND RESETS SYSRSTI# System Reset/Power good. This input is low when the reset switch is depressed. Otherwise, it reflects the power supply’s power good signal. PWGD is asynchronous to all clocks, and acts as ...
Page 22
STPC® ATLAS CAS#[1:0] Column Address Strobe. There are two active-low column address strobe output signals. The CAS# signals drive the memory devices directly without any external buffering. MWE# Write Enable. Write enable specifies whether the memory access is a read ...
Page 23
IOCHRDY IO Channel Ready. IOCHRDY is the IO channel ready signal of the ISA bus and is driven as an output in response to an ISA master cycle targeted to the host bus or an internal register of the STPC ...
Page 24
STPC® ATLAS RMRTCCS# ROM/Real Time clock chip select. This pin is a multi-function pin. This signal is asserted if a ROM access is decoded during a memory cycle. It should be combined with MEMR# or MEMW# signals to properly access ...
Page 25
ENIF# ENIF. This output is used to activate/select a PC Card socket. EXT_DIR EXternal Transceiver Direction Control. This output is high during a read and low during a write. The default power up condition is write (low). Used for both ...
Page 26
STPC® ATLAS VSYNC Vertical Synchronisation Pulse. This is the vertical synchronization signal from the VGA controller. HSYNC Horizontal Synchronisation Pulse. This is the horizontal synchronization signal from the VGA controller. VREF_DAC DAC Voltage reference. This pin is an input driving ...
Page 27
CTS0#, CTS1# Input Clear to send. RTS0#, RTS1# Output Request to send. DTR0#, DTR1# Output Data terminal read. 2.2.14. KEYBOARD/MOUSE INTERFACE KBCLK, Keyboard Clock line. Keyboard data is latched by the controller on each negative clock edge produced on this ...
Page 28
STPC® ATLAS Table 2-4. Multiplexed Signals (on the same pin) IDE Pin Name SD[15:0] RTCAS DEV_CLK SA[3] SA[2:0] SMEMW# IOCS16# MASTER# MCS16# DACK_ENC [2:0] TC SA[7:4] ZWS# GPIOCS# IOCHCK# REF# IOW# IOR# MEMR# ALE AEN BHE# MEMW# SMEMR# DREQ_MUX#[1:0] Hi-Z ...
Page 29
Table 2-5. Signal value on Reset Signal Name CS#[0] MA[10:0], BA[0] RAS#[1:0], CAS#[1:0] MWE#, DQM[7:0] MD[63:0] PCI INTERFACE AD[31:0] CBE[3:0], PAR FRAME#, TRDY#, IRDY# STOP#, DEVSEL# PERR#, SERR# PCI_GNT#[2:0] ISA BUS INTERFACE ISAOE# RMRTCCS# LA[23:17] SA[19:0] SD[15:0] BHE#, MEMR# MEMW#, ...
Page 30
STPC® ATLAS Table 2-5. Signal value on Reset Signal Name COL_SEL I2C INTERFACE SCL / DDC[1] SDA / DDC[0] TFT INTERFACE TFT[R,G,B][5:0] TFTLINE, TFTFRAME TFTDE, TFTENVDD, TFTENVCC, TFTPWM Low TFTDCLK USB INTERFACE 1 USBDPLS[1:0] 1 USBDMNS[1:0] 1 POWERON SERIAL CONTROLLER ...
Page 31
Table 2-6. Pinout Pin# Pin Name D15 SYSRSETI# C15 SYSRSETO# AF21 XTALI AF22 XTALO AF23 PCI_CLKI AF24 PCI_CLKO E15 ISA_CLK A16 ISA_CLK2X AB18 OSC14M AB24 HCLK 1 AB25 DEV_CLK /FCS1# AC18 DCLK AF20 MCLKI AF19 MCLKO U5 MA[0] V1 MA[1] ...
Page 32
STPC® ATLAS Table 2-6. Pinout Pin# Pin Name Y3 CS#[2]/MA[11] Y4 CS#[3]/MA[12]/BA[1] T2 DQM[0] T4 DQM[1] Y5 DQM[2] AA2 DQM[3] T3 DQM[4] T5 DQM[5] AA1 DQM[6] AA3 DQM[7] B3 AD[0] A3 AD[1] C4 AD[2] B4 AD[3] A4 AD[4] D5 AD[5] ...
Page 33
Table 2-6. Pinout Pin# Pin Name 1 G25 SD[10] 1 G24 SD[11] 1 J22 SD[12] 1 J23 SD[13] 1 F26 SD[14] 1 F25 SD[15] 1 F23 IOCHRDY 1 D20 ALE 1 K25 BHE# 1 F24 MEMR# 1 A22 MEMW# 1 ...
Page 34
STPC® ATLAS Table 2-6. Pinout Pin# Pin Name AF12 TFTG4 AB13 TFTG5 AC13 TFTB0 AD13 TFTB1 AE13 TFTB2 AF13 TFTB3 AF14 TFTB4 AE14 TFTB5 AB14 TFTLINE AC14 TFTFRAME AF15 TFTDE AE15 TFTENVDD AD15 TFTENVCC AC15 TFTPWM AD14 TFTDCLK D21 OC ...
Page 35
Table 2-6. Pinout Pin# Pin Name E5 GND E22 GND F6 GND F8 GND F9 GND F10 GND F12 GND F14 GND F16 GND F18 GND F19 GND F21 GND H4 GND H21 GND H23 GND J6 GND L6 GND ...
Page 36
STPC® ATLAS 3 STRAP OPTION This chapter defines the STPC Atlas Strap Options and their locations. Some strap options Signal Designation MD1 MD2 HCLK Speed MD3 MD[4] PCI_CLKO Divisor MD[5] MCLK Synchro (see MD[6] PCI_CLKO Programming MD[7] MD[8] ISA / ...
Page 37
Signal Designation MD41 Reserved MD42 Reserved MD 43 Reserved MD 45 CPUCLK/HCKL Deskew Programming Reserved MD 48 Reserved MD 50 Internal UART2 (see MD 51 Internal UART1 (see MD 52 Internal Kbd / Mouse (see MD ...
Page 38
STPC® ATLAS 3.1 STRAP OPTION STRAP0 7 6 MD[7] MD[6] This register defaults to the values sampled on the MD pins after reset Bit Number Sampled Mnemonic Bits 7-6 MD[7:6] Bits 5-4 MD[9:8] Bit 3 Rsv Bit 2 MD[5] Bits ...
Page 39
STRAP REGISTER 1 This register is read only. STRAP1 7 6 MD[40] MD[14] This register defaults to the values sampled on the MD pins after reset Bit Number Sampled Mnemonic Bits 7-6 MD[40] & MD[14] Bits 5-1 Rsv Bit ...
Page 40
STPC® ATLAS 3.1.3 HCLK PLL STRAP REGISTER This register is read only. HCLK_STRAP0 7 6 RSV MD[26] This register defaults to the values sampled on the MD pins after reset Bit Number Sampled Mnemonic Bits 7-6 Rsv Bits 5-3 MD[26:24] ...
Page 41
STRAP REGISTER 2 This register is read only with the exception of bit 4 STRAP2 7 6 MD[53] MD[52] This register defaults to the values sampled on the MD pins after reset Bit Number Sampled Mnemonic Bit 7 MD[53] ...
Page 42
STPC® ATLAS 3.1.5 CPUCLK/HCKL DESKEW PROGRAMMING MD[45] MD[46] HCLK between 33MHz and 1 0 HCLK between 64MHz and 0 1 All other settings are reserved Note that these straps are not accessible by software. Table 3-1. Typical Strap Option Implementation ...
Page 43
Table 3-1. Typical Strap Option Implementation Signal MD35 MD36 Local Bus Boot Device Size MD37 MD38 MD40 MD41 MD42 CPUCLK/HCKL Deskew Programming Internal UART2 (see MD 51 Internal ...
Page 44
STPC® ATLAS 4 ELECTRICAL SPECIFICATIONS 4.1. INTRODUCTION The electrical specifications in this chapter are valid for the STPC Atlas. 4.2. ELECTRICAL CONNECTIONS 4.2.1. POWER/GROUND DECOUPLING Due to the high frequency of operation of the STPC Atlas necessary to ...
Page 45
DC CHARACTERISTICS Table 4-2. DC Characteristics Symbol Parameter V 3.3V Operating Voltage DD V 2.5V Operating Voltage CORE P 3.3V Supply Power 2.5V Supply Power CORE V Input Low Voltage IL V Input High Voltage IH ...
Page 46
STPC® ATLAS Table 4-4. RAMDAC DC Specification Symbol Vref_dac Voltage Reference INL Integrated Non Linear Error DNL Differentiated Non Linear Error BLC Black Level Current WLC White Level Current Table 4-5. VGA RAMDAC Power Consumption DCLK (MHz) - 6.25 - ...
Page 47
AC CHARACTERISTICS This section lists the AC characteristics of the STPC interfaces including output delays, input setup requirements, input hold requirements and output float delays. These measurements are based on the measurement points identified in Figure 4-1 and Figure ...
Page 48
STPC® ATLAS 4.5.1. POWER ON SEQUENCE Figure 4-2. CLK Timing Measurement Points (MIN) V Ref V IL (MAX) CLK One Clock Cycle LEGEND Minimum Time Minimum Time at ...
Page 49
Figure 4-3. Power-on timing diagram Power Supplies 14 MHz SYSRSTI# ISACLK Strap Options HCLK PCI_CLK SYSRSTO# > 1.6 V VALID CONFIGURATION 2.3 ms STPC® ATLAS 49/108 1 ...
Page 50
STPC® ATLAS 4.5.2 RESET SEQUENCE Figure 4-4 describes the reset sequence of the STPC, also called warm reset. The constraints on the strap options and the bus activities are the same as for the cold reset. The SYSRSTI# pulse duration ...
Page 51
SDRAM INTERFACE Figure 4-5, Table 4-10, Table 4-11 characteristics of the SDRAM interface. The Figure 4-5. SDRAM Timing Diagram MCLKx MCLKI STPC.output STPC.input Thold Table 4-10. SDRAM Bus AC Timings - Commercial Temperature Range Name Parameter Tcycle MCLKI Cycle ...
Page 52
STPC® ATLAS Table 4-11. SDRAM Bus AC Timings - Industrial Temperature Range Name Parameter Tcycle MCLKI Cycle Time Thigh MCLKI High Time Tlow MCLKI Low Time MCLKI Rising Time MCLKI Falling Time Tdelay MCLKx to MCLKI delay MCLKI to RAS# ...
Page 53
PCI INTERFACE Figure 4-6 and Table 4-12. list the AC characteris- tics of the PCI interface. PCICLKx stands for any PCI device clock input. Figure 4-6. PCI Timing Diagram HCLK PCICLKx PCICLKI Thclk STPC.output STPC.input Thold Table 4-12. PCI ...
Page 54
STPC® ATLAS 4.5.5 IPC INTERFACE Table 4-13 lists the AC characteristics of the IPC interface. Figure 4-7. IPC timing diagram ISACLK2X ISACLK IRQ_MUX[3:0] DREQ_MUX[1:0] Table 4-13. IPC Interface AC Timings Name Parameter T IRQ_MUX[3:0] Input setup to ISACLK2X setup T ...
Page 55
ISA INTERFACE AC TIMING CHARACTERISTICS Figure 4-8 and Table 4-14 list the AC characteris- tics of the ISA interface. Figure 4-8. ISA Cycle (ref Table ALE AEN LA [23:17] Valid Address SA [19:0] CONTROL (Note 1) IOCS16# MCS16# IOCHRDY ...
Page 56
STPC® ATLAS Table 4-14. ISA Bus AC Timing Name Parameter 10c Memory access to 16-bit ISA Slave 10d Memory access to 8-bit ISA Slave 10e SA[19:0] & SBHE valid before IOR#, IOW# asserted 11 ISACLK2X to IOW# valid 11a Memory ...
Page 57
Table 4-14. ISA Bus AC Timing Name Parameter 24i Memory access to 16-bit ISA Slave - 4BCLK 24k Memory access to 8-bit ISA Slave - 3BCLK 24l Memory access to 8-bit ISA Slave Standard cycle 24 IOR#, IOW# asserted before ...
Page 58
STPC® ATLAS Table 4-14. ISA Bus AC Timing Name Parameter 38 ALE# asserted to read data valid 38b Memory access to 16-bit ISA Slave Standard Cycle 38e Memory access to 8-bit ISA Slave Standard Cycle 38h I/O access to 16-bit ...
Page 59
Table 4-14. ISA Bus AC Timing Name Parameter 61e I/O access to 16-bit ISA Slave 61f I/O access to 8-bit ISA Slave 64a MEMW# negated to write data invalid - 16-bit 64b MEMW# negated to write data invalid - 8-bit ...
Page 60
STPC® ATLAS 4.5.7. LOCAL BUS INTERFACE Figure 4-3 to Figure 4-12 and AC characteristics of the Local Bus interface. Figure 4-9. Synchronous Read Cycle HCLK PA[ ] bus Tsetup CSx# BE#[1:0] PRD# PD[15:0] 60/108 1 Table 4-16 list the Tactive ...
Page 61
Figure 4-10. Asynchronous Read Cycle HCLK PA[ ] bus Tsetup CSx# BE#[1:0] PRD# PD[15:0] PRDY Figure 4-11. Synchronous Write Cycle HCLK PA[ ] bus Tsetup CSx# BE#[1:0] PWR# PD[15:0] Tend Thold Tactive Thold STPC® ATLAS 61/108 1 ...
Page 62
STPC® ATLAS Figure 4-12. Asynchronous Write Cycle HCLK PA[ ] bus Tsetup CSx# BE#[1:0] PWR# PD[15:0] PRDY The Table 4-15. below refers to Vh, Va, Vs which are the register value for Setup time, Active Time Table 4-15. Local Bus ...
Page 63
PCMCIA INTERFACE Table 4-17 lists the AC characteristics of the PCMCIA interface. Table 4-17. PCMCIA Interface AC Timing Name Parameters t27 Input setup to ISACLK2X t28 Input hold from ISACLK2X t29 ISACLK2X to IORD t30 ISACLK2X to IORW t31 ...
Page 64
STPC® ATLAS 4.5.9 IDE INTERFACE Figure 4-13, Figure 4-14 and AC characteristics of the IDE interface. Figure 4-13. IDE PIO timing diagram CS#,DA[2:0] DIOR#,DIOW# DD[15:0] IORDY Figure 4-14. IDE DMA timing diagram CS# REQ ACK# DIOR#,DIOW# DD[15:0] read DD[15:0] write ...
Page 65
TFT INTERFACE Table 4-19 lists the AC characteristics of the TFT interface. Table 4-19. TFT Interface Timings Name Parameters DCLK (input) to R[5:0], G[5:0], B[5;0] DCLK (input) to FPLINE DCLK (input) to FPFRAME DCLK (output) to R[5:0], G[5:0], B[5;0] ...
Page 66
STPC® ATLAS 4.5.14 JTAG INTERFACE Figure 4-15 lists the AC characteristics of the JTAG interface. Table 4-23. JTAG AC Timings Name Parameter Treset TRST pulse width Tcycle TCLK period TCLK rising time TCLK falling time Tjset TMS setup time Tjhld ...
Page 67
MECHANICAL DATA 5.1. 516-PIN PACKAGE DIMENSION The pin numbering for the STPC 516-pin Plastic BGA package is shown in Figure Figure 5-1. 516-Pin PBGA Package - Top View ...
Page 68
STPC® ATLAS Figure 5-2. 516-pin PBGA Package - PCB Dimensions A1 Ball Pad Corner A Table 5-1. 516-pin PBGA Package - PCB Dimensions Symbols Min A 34.80 B 1.22 C 0.60 D 1.57 E 0.15 68/108 ...
Page 69
Table 5-1. 516-pin PBGA Package - PCB Dimensions F 0.05 G 0.75 Figure 5-3. 516-pin PBGA Package - Dimensions C Solderball A Table 5-2. 516-pin PBGA Package - Dimensions Symbols Min A 0.50 B 1.12 C 0.60 D 0.52 E ...
Page 70
STPC® ATLAS 5.2. 516-PIN PACKAGE THERMAL DATA 516-pin PBGA package has a Power Dissipation Capability of 4.5W which increases to 6W when used with a Heatsink. Figure 5-4. 516-Pin PBGA Structure Signal layers Figure 5-5. Thermal Dissipation Without Heatsink Board ...
Page 71
Figure 5-6. Thermal Dissipation With Heatsink Board Ambient Rca Case Rjc Junction Rjb Board Rba Ambient Junction 3 6 Board Case 8.5 50 Ambient Rja = 9.5 °C/W STPC® ATLAS Board dimensions ...
Page 72
STPC® ATLAS 5.3. SOLDERING RECOMMENDATIONS High quality, low defect soldering requires identifying the optimum temperature profile for reflowing the solder paste, therefore optimizing the process. The heating and cooling rise rates must be compatible with the solder paste and components. ...
Page 73
DESIGN GUIDELINES 6.1. TYPICAL APPLICATIONS The STPC Atlas is well suited for many applications. Some of implementations are described below. 6.1.1. THIN CLIENT A Thin-Client is a terminal running ICA TM or RDP (Microsoft) protocol. The display is computed ...
Page 74
STPC® ATLAS 6.1.2. INTERNET TERMINAL The internet terminal described here is an optimized implementation where the STPC Atlas board is integrated into the CRT itself. The advantages are a reduced overall cost and a good image definition. The STPC Atlas ...
Page 75
STPC CONFIGURATION The STPC is a very flexible product thanks to decoupled clock domains and to strap options enabling a user-optimized configuration. As some trade off are often necessary important analysis of the application ...
Page 76
STPC® ATLAS 6.3.1. POWER DECOUPLING An appropriate decoupling of the various STPC power pins is mandatory for optimum behaviour. When insufficient, the integrity of the signals is deteriorated, the stability of the system is reduced and EMC is increased. 6.3.1.1. ...
Page 77
SDRAM The STPC provides all the signals for SDRAM control 128 MBytes of main memory are supported. All Banks must be 64 bits wide memory banks are available when using 16Mbit devices. Only up ...
Page 78
STPC® ATLAS Figure 6-6. One Memory Banks with 8 Chips (8-bit) MCLKI 10pF MCLKO CY2305 CS0# MA[12:0] BA[1:0] RAS0# CAS0# WE# DQM[7:0] MD[63:0] Refer to Section 4.5.3. for detailed timing constraints. 78/108 1 Length(MCLKI+1ns(+/- 0.5ns)) = Length(MCLKx ...
Page 79
Figure 6-7. Two Memory Banks with 8 Chips (8-bit) MCLKI 22pF MCLKO CY2305 CS1# CS0# MA[12:0] BA[1:0] RAS0# CAS0# WE# DQM[7:0] MD[63:0] Refer to Section 4.5.3. for detailed timing constraints. Table 6-4. DIMM Pinout SDRAM Density Internal Banks DIMM Pin ...
Page 80
STPC® ATLAS 6.3.4. PCI BUS The PCI bus is always active and the following control signals must be pulled- through 8K2 resistors even if this bus is not connected to an external device: FRAME#, TRDY#, IRDY#, ...
Page 81
LOCAL BUS The local bus has all the signals to directly connect flash devices or I/O devices. Figure 6-10. Typical 16-bit boot flash implementation 22 PA[22:1] FCS0# PRD# PWR# 16 PD[15:0] SYSRSTI# STPC Figure 6-10 describes how to connect ...
Page 82
STPC® ATLAS 6.3.6. IPC Most of the IPC signals are multiplexed: Interrupt inputs, DMA Request inputs, DMA Acknowledge outputs. The figure below describes a complete implementation of the IRQ[15:0] time-multiplexing. Figure 6-11. Typical IRQ multiplexing Timer 0 Keyboard Slave PIC ...
Page 83
The figure below describes implementation of the external glue logic for DMA Request time-multiplexing and DMA Acknowledge demultiplexing. Like for the interrupt lines, this Figure 6-12. Typical DMA multiplexing and demultiplexing ISA, Refresh ISA, PIO ISA, FDC ISA, PIO Slave ...
Page 84
STPC® ATLAS 6.3.7. IDE / ISA DYNAMIC DEMULTIPLEXING Some of the ISA bus signals are dynamically multiplexed to optimize the pin count. Figure 6-13. Typical IDE / ISA Demultiplexing STPC bus / DD[15:0] 6.3.8. BASIC AUDIO USING IDE INTERFACE When ...
Page 85
VGA INTERFACE The STPC integrates a voltage reference and video buffers. The amount of external devices is then limited to the minimum as described in the Figure 6-15. All the resistors and capacitors have close as ...
Page 86
STPC® ATLAS 6.3.10. USB INTERFACE The STPC integrates a USB host interface with a 2-port Hub. The only external device needed are Figure 6-16. Typical USB implementation USBDMNS[0] USBDPLS[0] USBDMNS[1] USBDPLS[1] OC POWERON STPC Note 1: The ESD protection will ...
Page 87
KEYBOARD/MOUSE INTERFACE The STPC integrates a PC/AT+ keyboard and PS/ 2 mouse controller. The only external devices Figure 6-17. Typical Keyboard / Mouse implementation MDATA MCLK KBDATA KBCLK STPC needed are the ESD KBMF01SC6. Figure 6-17 implementation using a ...
Page 88
STPC® ATLAS 6.3.12. PARALLEL PORT INTERFACE The STPC integrates a parallel port where the only external device needed is the ESD protection Figure 6-18. Typical parallel port implementation ACK# BUSY PE SLCT SLCTIN# INIT# ERR# AUTOFD# STROBE# PD[7:0] STPC 88/108 ...
Page 89
JTAG INTERFACE The STPC integrates a JTAG interface for scan- chain and on-board testing. The only external Figure 6-19. Typical JTAG implementation TCLK TDO TMS TDI TRST STPC 6.4. PLACE AND ROUTE RECOMMENDATIONS 6.4.1. GENERAL RECOMMENDATIONS Some STPC Interfaces ...
Page 90
STPC® ATLAS Figure 6-20. Shielding signals ground pad 90/108 1 ground ring shielded signal line ground pad shielded signal lines ...
Page 91
MEMORY INTERFACE 6.4.3.1. Introduction In order to achieve SDRAM memory interfaces which work at clock frequencies of 90 MHz and above, careful consideration has to be given to the timing of the interface with all the various electrical and ...
Page 92
STPC® ATLAS Figure 6-22. DIMM placement SDRAM components and the memory controller will impact the timing budget. In order to get well matched clocks at all components recommended that all the DIMM clock pins, STPC memory clock input (MCLKI) and ...
Page 93
The maximum skew between pins for this part is 250ps. The important factors for the clock buffer are a consistent drive strength and low skew between the outputs. The delay through the buffer is not important so it does not ...
Page 94
STPC® ATLAS Figure 6-25. IBIS Simulation for on-board SDRAM / 90MHz (V) 3 MCLKI MCLKO 2 1 6.5.0.1. Clock topology for standard DIMM Figure 6-26 and Figure 6-27 give the recommend- ed clock topology and the resulting IBIS simulation Figure ...
Page 95
Figure 6-27. IBIS Simulation for DIMM / 90MHz (V) 3 MCLKI Buffer output 2 1 MCLKx 2.0 V 1.40 ns 0.8 V STPC® ATLAS 1.20 ns Time 95/108 ...
Page 96
STPC® ATLAS 6.5.1. PCI INTERFACE 6.5.1.1. Introduction In order to achieve a PCI interface which work at clock frequencies up to consideration has to be given to the timing of the interface with all the various electrical and physical constraints ...
Page 97
Figure 6-28. Clock Scheme HCLK PLL clock delay Deskewer South Bridge North Bridge HCLK PCICLKO 1/2 1/3 1/4 PCICLKI AD[31:0] MUX STPC STPC® ATLAS 97/108 ...
Page 98
STPC® ATLAS Figure 6-29. Typical PCI clock routing PCICLKI PCICLKO Note: The value of 22 Ohms corresponds to tracks with Z Figure 6-30. Clocks relationships HCLK PCICLKO PCICLKI PCICLKx 98/108 Length(PCICLKI) = Length(PCICLKx) with x = {A,B,C} PCICLKA Device A ...
Page 99
THERMAL DISSIPATION 6.5.2.1. Power saving Thermal dissipation of the STPC depends mainly on supply voltage. When the system does not need to work at the upper voltage limit, it may therefore be beneficial to reduce the voltage to the ...
Page 100
STPC® ATLAS When considering thermal dissipation, one of the most important parts of the layout is the connection between the ground balls and the ground layer. Figure 6-32. Recommended 1-wire Power/Ground Pad Layout Considering only the central matrix of 36 ...
Page 101
To avoid solder wicking over to the via pads during soldering important to have a solder mask of 4 mil around the pad (NSMD pad). This gives a diameter of 33 mil for a 25 mil ground pad. ...
Page 102
STPC® ATLAS As the PCB acts as a heat sink, the layout of top and ground layers must be done with care to maximize the board surface dissipating the heat. The only limitation is the risk of losing routing channels. ...
Page 103
Figure 6-37. Recommend signal wiring (top & ground layers) with corresponding heat flow GND Power GND Power STPC® ATLAS Power/GND balls Internal row Signal balls External row Keep-Out = 6 mils Power/GND balls Signal balls 103/108 ...
Page 104
STPC® ATLAS 6.6. DEBUG METHODOLOGY In order to bring a STPC-based board to life with the best efficiency recommended to follow the check-list described in this section. 6.6.1. POWER SUPPLIES In parallel with the assembly process ...
Page 105
POST code Once the 16 first bytes are fetched and decoded, the CPU core continue its execution depending on the content of these first data. Usually, it corresponds to a JUMP instruction and the code fetching continues, generating read ...
Page 106
STPC® ATLAS Check: Measure HCLK is at selected frequency 5 HCLK 25MHz < HCLK < 66MHz Measure PCICLKO: - maximum is 33MHz by standard - check selected frequency 6 PCI clocks - it is generated from HCLK ...
Page 107
... ORDERING DATA 7.1. ORDERING CODES STMicroelectronics Prefix Product Family PC: PC Compatible Product ID I2: Atlas Core Speed G: 120 MHz H: 133 MHz Memory Speed D: 90 MHz E: 100 MHz Package Y: 516 Overmoulded BGA Temperature Range C: Commercial Tcase = 0 to +85°C I: Industrial Tcase = -40 to +115°C 7 ...
Page 108
... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...