LH7A400N0F000B5 NXP Semiconductors, LH7A400N0F000B5 Datasheet
LH7A400N0F000B5
Specifications of LH7A400N0F000B5
Available stocks
Related parts for LH7A400N0F000B5
LH7A400N0F000B5 Summary of contents
Page 1
... CORE PART NUMBER CLOCK 250 MHz/ LH7A400N0F076B5 245 MHz 200 MHz/ LH7A400N0F000B3A 195 MHz 200 MHz/ LH7A400N0F000B5 195 MHz 200 MHz/ LH7A400N0G000B5 195 MHz Preliminary data sheet 32-Bit System-on-Chip • Three Programmable Timers • Three UARTs – Classic IrDA (115 kbit/s) • ...
Page 2
... LH7A400 Type number LH7A400N0G000B5 BGA256 LH7A400N0F000B3A LFBGA256 LH7A400N0F000B5 LFBGA256 LH7A400N0F076B5 LFBGA256 2 NXP Semiconductors Table 2. Ordering information Package Name Description plastic ball grid array package; 256 balls plastic low profile fine-pitch ball grid array package; 256 balls plastic low profile fine-pitch ball grid array package ...
Page 3
... INTERFACE SYNCHRONOUS DYNAMIC RAM CONTROLLER (SDMC) LCD AHB BUS COLOR LCD CONTROLLER ADVANCED LCD INTERFACE HIGH-PERFORMANCE Preliminary data sheet NXP Semiconductors 14.7456 MHz 32.768 kHz OSCILLATOR, PLL1 and PLL2, POWER MANAGEMENT, and RESET CONTROL INTERRUPT CONTROLLER ADVANCED PERIPHERAL BUS BRIDGE 80KB ...
Page 4
... LH7A400 4 NXP Semiconductors LH7A400 ball A1 index area Transparent top view Figure 2. Pin configuration (BGA256) LH7A400 ball A1 index area Transparent top view Figure 3. Pin configuration (LFBGA256) Rev. 01 — 16 July 2007 32-Bit System-on-Chip 002aad223 002aad224 Preliminary data sheet ...
Page 5
... F4 K9 F10 VDDC Core Power L13 J4 E15 J8 D12 T10 L4 N15 L9 VSSC Core Ground H12 N3 B15 N7 C9 N10 G6 R5 Preliminary data sheet NXP Semiconductors Table 3. Functional Pin List RESET DESCRIPTION STATE Rev. 01 — 16 July 2007 LH7A400 STANDBY OUTPUT I/O NOTES STATE DRIVE 5 ...
Page 6
... D14 D14 D21 F10 E12 D22 A16 B16 D23 A14 D12 D24 B13 A16 D25 6 NXP Semiconductors Table 3. Functional Pin List (Cont’d) DESCRIPTION Rev. 01 — 16 July 2007 32-Bit System-on-Chip RESET STANDBY OUTPUT I/O NOTES STATE STATE DRIVE Input No Change I Input ...
Page 7
... Sync Memory Clock Enable 3 A10 B10 SCLK Sync Memory Clock C14 C13 nSCS0 Sync Memory Chip Select 0 Preliminary data sheet NXP Semiconductors Table 3. Functional Pin List (Cont’d) DESCRIPTION LOW: A25 LOW: A26 LOW: A27 LOW: CS6 LOW: CS7 Rev. 01 — 16 July 2007 LH7A400 ...
Page 8
... PC3/LCDREV • HR-TFT Gray Scale Voltage Reverse PC4/ • GPIO Port LCDSPS • HR-TFT Reset Row Driver Counter 8 NXP Semiconductors Table 3. Functional Pin List (Cont’d) DESCRIPTION Input: PA0 Input: PA1 Input: PB0 Input: PB1 Input: PB2 Input: PB3 Input: PB4 ...
Page 9
... GPIO Port PG1/nPCWE • Write Enable for PC Card (PCMCIA or CF) in sin- gle or dual card mode Preliminary data sheet NXP Semiconductors Table 3. Functional Pin List (Cont’d) DESCRIPTION LOW: PC5 LOW: PC6 LOW: PC7 LOW: PD0 LOW: PD1 ...
Page 10
... R6 T7 LCDFP LCD Frame Synchronization pulse R8 R9 LCDLP LCD Line Synchronization pulse 10 NXP Semiconductors Table 3. Functional Pin List (Cont’d) DESCRIPTION LOW: PG2 LOW: PG3 LOW: PG4 LOW: PG5 LOW: PG6 LOW: PG7 Input: PH0 Input: PH1 ...
Page 11
... Synchronous Serial Port Receive J2 J7 SSPTX Synchronous Serial Port Transmit SSPFRM Synchronous Serial Port Frame Sync nSSPFRM Preliminary data sheet NXP Semiconductors Table 3. Functional Pin List (Cont’d) DESCRIPTION LCDENAB MMCCLK MMCCMD MMCDATA Rev. 01 — 16 July 2007 LH7A400 RESET STANDBY OUTPUT ...
Page 12
... All unused USB Device pins with a differential pair must be pulled Ω to ground with resistor. Table 4. nTest Pin Function MODE nTEST0 nTEST1 JTAG 0 1 Normal NXP Semiconductors Table 3. Functional Pin List (Cont’d) DESCRIPTION Ω nURESET 1 x Rev. 01 — 16 July 2007 32-Bit System-on-Chip RESET STANDBY OUTPUT I/O NOTES STATE STATE ...
Page 13
... LCDVD1 MUSTN1 P7 M8 LCDVD0 MUSTN0 Notes: 1. The Intensity bit is identically generated for all three colors Monochrome Upper Color Upper Color Lower Preliminary data sheet NXP Semiconductors Table 5. LCD Data Multiplexing STN MONO 8-BIT DUAL SINGLE DUAL SINGLE PANEL PANEL PANEL PANEL ...
Page 14
... C3 MEDCHG C4 ACBITCLK C5 PF7/INT7/PCRDY2 C6 PF2/INT2 C7 PWM0 C8 nWE0 C9 VSSC C10 CS7/SCKE0 C11 nCAS C12 nSWE C13 D26 14 NXP Semiconductors Table 6. 256-Ball BGA Package Numerical Pin List (Cont’d) BGA PIN C14 nSCS0 C15 VSS C16 A21 D1 BATOK D2 nBATCHG D3 nPOR D4 WAKEUP D5 ACOUT D6 PF5/INT5/SCDETECT D7 nPWME1 ...
Page 15
... A11/SA9 H15 D11 H16 A10/SA8 J1 SSPRX J2 SSPTX J3 SSPFRM/nSSPFRM J4 VDDC J5 PA0/LCDVD16 J6 PGMCLK J7 UARTRX2 Preliminary data sheet NXP Semiconductors Table 6. 256-Ball BGA Package Numerical Pin List (Cont’d) BGA PIN J8 A6/SA4 J9 A9/SA7 J10 D10 J11 VDD J12 VDD J13 D9 J14 A8/SA6 J15 D8 J16 ...
Page 16
... P5 PH5/CFA10/PCMCIAA24/nPCWAIT2 P6 VSS P7 LCDVD0 P8 PH4/nPCWAIT1 P9 LCDENAB/LCDM P10 PD6/LCDVD14 P11 WIDTH0 P12 VSSA P13 nCS2 P14 CLKEN P15 XTAL32OUT 16 NXP Semiconductors Table 6. 256-Ball BGA Package Numerical Pin List (Cont’d) BGA PIN P16 XTAL32IN R1 PC2/LCDVDDEN R2 PC7/LCDSPL R3 PG0/nPCOE R4 PH1/CFA8/PCRESET2 R5 PH6/nAC97RESET R6 LCDFP R7 LCDVD1 R8 LCDLP R9 PD4/LCDVD12 ...
Page 17
... MMCCLK/MMSPICLK C4 VDDC C5 PF4/INT4/SCVCCEN C6 VSS C7 nPWME0 C8 nOE C9 DQM0 C10 VDD C11 nRAS C12 D28 C13 nSCS0 Preliminary data sheet NXP Semiconductors Table 7. 256-Ball LFBGA Package Numerical Pin List LFBGA PIN C14 A22 C15 A21 C16 A20 D1 nURESET D2 nEXTPWR D3 TDO D4 MMCDATA/MMSPIDOUT D5 VSS D6 PF5/INT5/SCDETECT ...
Page 18
... H11 D11 H12 A11/SA9 H13 VDD H14 D10 H15 A9/SA7 H16 D9 J1 TBUZ J2 SSPFRM/nSSPFRM J3 SSPCLK J4 VDDC J5 PGMCLK 18 NXP Semiconductors Table 7. 256-Ball LFBGA Package Numerical Pin List LFBGA PIN J6 SSPRX J7 SSPTX J8 VDDC J9 VDD J10 D8 J11 A7/SA5 J12 D7 J13 A6/SA4 J14 VSS J15 ...
Page 19
... PC4/LCDSPS P4 PG2/nPCIOR P5 PG5/nPCCE1 P6 PH0/PCRESET1 P7 PH6/AC97RESET P8 LCDVD1 P9 LCDENAB/LCDM P10 PD2/LCDVD10 P11 VDD P12 VDDA P13 nTEST1 Preliminary data sheet NXP Semiconductors Table 7. 256-Ball LFBGA Package Numerical Pin List LFBGA PIN P14 nCS0 P15 nTEST0 P16 nCS1 R1 PC2/LCDVDDEN R2 PC6/LCDHRLP R3 PG3/nPCIOW R4 PG6/nPCCE2 R5 VSSC R6 PH4/nPCWAIT1 ...
Page 20
... The amount of clock gating that actually takes place is dependent on the current power saving mode selected. 20 NXP Semiconductors TOUCH SCREEN CONTR ...
Page 21
... Standby mode. Once in Run mode the PWRSR register can be interrogated to deter- mine the nature of the reset, and the trigger source, after which software can then take appropriate actions. Preliminary data sheet NXP Semiconductors FCLK STATE CONTROLLER HCLK (TO PROCESSOR CORE) ...
Page 22
... Part of the remaining memory space is allocated to the embedded SRAM, and to the control registers of the AHB and APB. The rest is unused. 22 NXP Semiconductors The LH7A400 can boot from either synchronous or asynchronous ROM/Flash. The selection is determined by the value of the MEDCHG pin at Power On Reset as shown in Table 8 ...
Page 23
... The LCD con- troller is designed to automatically use an overflow frame buffer in SDRAM if a larger screen size is required. This overflow buffer can be located on any Preliminary data sheet NXP Semiconductors SYNCHRONOUS MEMORY (nSCS3) SYNCHRONOUS MEMORY (nSCS2) SYNCHRONOUS MEMORY (nSCS1) SYNCHRONOUS MEMORY (nSCS0) ...
Page 24
... LH7A400 EXTERNAL TO INTERNAL TO THE LH7A400 THE LH7A400 SDRAM SRAM ADDRESS SDRAM ROM CONTROL Figure 7. External Bus Interface Block Diagram 24 NXP Semiconductors ARM922T ASYNCHRONOUS STATIC MEMORY CONTROLLER (SMC) EXTERNAL DATA PCMCIA/CF BUS SUPPORT INTERFACE (EBI) and SYNCHRONOUS DYNAMIC MEMORY CONTROLLER (SDMC) 80KB ...
Page 25
... MMC card, and to configure and acquire status information from the card’s registers. Preliminary data sheet NXP Semiconductors MMC bus lines can be divided into three groups: • Power supply: VDD and VSS • Data Transfer: MMCCMD, MMCDATA • ...
Page 26
... Compatible with both OpenHCI and Intel’s UHCI standards • Supports full-speed (12 Mbps) functions • Supports Suspend and Resume signalling. 26 NXP Semiconductors Color LCD Controller The LH7A400’s LCD Controller is programmable to support up to 1,024 × 768, 16-bit color LCD panels. It interfaces directly to STN, color STN, TFT, AD-TFT, and HR-TFT panels. Unlike other LCD controllers, the LH7A400’ ...
Page 27
... Parallel-to-Serial conversion on data transmitted to the peripheral device. Preliminary data sheet NXP Semiconductors The transmit and receive paths are buffered with inter- nal FIFO memories allowing bytes to be stored independently in both transmit and receive modes. The UART can generate: • ...
Page 28
... Since more than one device may attempt to take control of the bus as a master, SMBus provides an arbitration mechanism, by relying on the wired-AND connection of all SMBus interfaces to the SMBus. 28 NXP Semiconductors DC-to-DC Converter The features of the DC-DC Converter interface are: • Dual drive PWM outputs, with independent closed loop feedback • ...
Page 29
... VDDC = 1. 1.89 V (LH7A400N0G000xx) ± 5. VDDC = 2 (LH7A400N0G076xx only) 6. VDD = 3 3.6 V (LH7A400N0G000xx) 7. VDD = 3.14V to 3.60 V (LH7A400N0G076xx only) 8. IMPORTANT: Most peripherals will NOT function with crystals other than 14.7456 MHz. Preliminary data sheet NXP Semiconductors MINIMUM MAXIMUM −0.3 V −0.3 V −0.3 V −0.5 V −55°C MINIMUM TYPICAL 1 ...
Page 30
... Clock Frequency (FCLK) 70°C Clock Period (FCLK) Clock Frequency (FCLK) 85°C Clock Period (FCLK) NOTES: 1. Table 9 is representative of a typical wafer process. Guaranteed values are in the Recommended Operating Conditions table. 2. LH7A400N0G000xx 30 NXP Semiconductors ° TEMP ( C) (For LH7A400N0G000xx) 1.71 V 1.8 V 1.89 V 211 MHz ...
Page 31
... Current consumption until oscillators are stabilized. AC Test Conditions PARAMETER DC I/O Supply Voltage (VDD) DC Core Supply Voltage (VDDC) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Preliminary data sheet NXP Semiconductors MIN. TYP. MAX. UNIT 2.0 5.5 − 0.2 0.8 0.25 2 ...
Page 32
... I/O loads at nominal • Cache enabled • FCLK = 200 MHz or 250 MHz; HCLK = 100 MHz or 125 MHz; PCLK = 50 MHz or 62.5 MHz • All voltages at typical values • Nominal case temperature (tAMB). 32 NXP Semiconductors Table 10. Current Consumption by Mode SYMBOL PARAMETER ICORE Core Current IIO ...
Page 33
... OUTPUT SIGNAL (O) INPUT SIGNAL (I) Preliminary data sheet NXP Semiconductors • ACBITCLK, AC97 clock • SCLK, Synchronous Memory clock. All signal transitions are measured at the 50 % point. For outputs from the LH7A400, tOVXXX (e.g. tOVA) represents the amount of time for the output to become valid from a valid address bus, or rising edge of the peripheral clock ...
Page 34
... Output 30 pF nPCOE Output 30 pF nPCWE Output 30 pF PCDIR Output NXP Semiconductors Table 12. AC Signal Characteristics MIN. MAX. tRC 4 × tHCLK – 7 × tHCLK + 7.5 ns tWC 4 × tHCLK – 7 × tHCLK + 7.5 ns tWS tHCLK ns tHCLK ns tDVWE tHCLK – 6.0 ns tHCLK – ...
Page 35
... ACIN Input LCDVD [17:0] Output 30 pF NOTES: 1. Register BCRx:WST1 = 0b000 2. For Output Drive strength specifications, refer to Table 3 3. LH7A400N0G076xx only 4. LH7A400N0G000xx only Preliminary data sheet NXP Semiconductors MIN. MAX. MMC INTERFACE SIGNALS tOS 5 ns tOH 5 ns tOS 5 ns tOH 5 ns ...
Page 36
... D[31:0] nCSx nWE nBLE Figure 10. External Asynchronous Memory Write with 0 Wait States (BCRx:WST1 = 0b000) 36 NXP Semiconductors deassertion of nCS by a maximum of one HCLK minimum, can coincide (see Table 12). Figure 12 and Figure 13 show the waveform and timing for an Exter- nal Asynchronous Memory Read. 1 ...
Page 37
... System-on-Chip 0 1 HCLK A[27:0] D[31:0] nCSx nWE nBLE 0 WAIT STATE Figure 11. External Asynchronous Memory Write with 4 Wait States (BCRx:WST1 = 0b100) Preliminary data sheet NXP Semiconductors VALID ADDRESS VALID DATA nCSx Valid nWE Valid nBLE Valid WAIT WAIT WAIT WAIT STATE 1 ...
Page 38
... LH7A400 0 HCLK A[27:0] D[31:0] nCSx nOE nBLE Figure 12. External Asynchronous Memory Read with 0 Wait States (BCRx:WST1 = 0b000) 38 NXP Semiconductors tRC tAHCS, tAHOE, tAHBE VALID ADDRESS VALID DATA tDSCS tAVCS tCS nCS Valid tDSOE tAVOE tOE nOE Valid tDSBE tAVBE tBER nBLE Valid Rev. 01 — ...
Page 39
... SSP is idle. The SSP serial clock tran- sitions only during active transmission of data. The SSPFRM signal marks the beginning and end of a frame. The SSPEN signal controls an off-chip line driver’s output enable pin. Preliminary data sheet NXP Semiconductors ...
Page 40
... NOTES: 1. SDRAMcmd is the combination of nRAS, nCAS, nSWE, and nSCSx. 2. tOVXXX represents tOVRA, tOVCA, tOVSVW, or tOVSC. Refer to the AC timing table. 3. tOHXXX represents tOHRA, tOHCA, tOHSVW, or tOHSC. Figure 15. Synchronous Bank Activate and Write 40 NXP Semiconductors t OHXXX READ t OHA, tOHB t OVXXX BANK, tISD tIHD ...
Page 41
... Figure 17. Texas Instruments Synchronous Serial Frame Format (Continuous Transfer) SSPCLK nSSPFRM SSPRXD MSB MSB SSPTXD NOTE undefined. Figure 18. Motorola SPI Frame Format (Single Transfer) with SPO = 0 and SPH = 0 Preliminary data sheet NXP Semiconductors MSB LSB BITS MSB BITS BITS Rev. 01 — 16 July 2007 LH7A400 LH7A400-97 ...
Page 42
... SSPTXD/ SSSRXD Figure 21. Motorola SPI Frame Format (Continuous Transfer) with SPO = 0 and SPH = 1 SSPCLK nSSPFRM SSPTXD/ SSSRXD Figure 22. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 1 42 NXP Semiconductors MSB BITS BITS LSB MSB BITS LSB MSB BITS Rev. 01 — ...
Page 43
... Figure 24. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 0 SSPCLK nSSPFRM SSPRXD Q MSB SSPTXD MSB NOTE undefined. Figure 25. Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 1 Preliminary data sheet NXP Semiconductors BITS MSB LSB BITS BITS Rev. 01 — 16 July 2007 LH7A400 LSB Q LSB ...
Page 44
... MSB BITS OUTPUT DATA Figure 27. MICROWIRE Frame Format (Continuous Transfers) 44 NXP Semiconductors an 8-bit control message is transmitted to the off-chip slave. During this transmission no incoming data is received by the SSP. After the message has been sent, the external slave device decodes the message. After ...
Page 45
... TRANSFER TYPE 0 0 Common Memory 0 1 Attribute Memory None Preliminary data sheet NXP Semiconductors PRECHARGE ACCESS TIME TIME (See Note 1) (See Note 1) (See Note 1) ADDRESS tOVDREG tOHDREG tOVCEx tOHCEx tOVPCD tOHPCD DATA tISD tIHD ...
Page 46
... TRANSFER TYPE 0 0 Common Memory 0 1 Attribute Memory None nPCWE, nPCOE nCSx Figure 30. PCMCIA Precharge, Access, and Hold Waveform 46 NXP Semiconductors PRECHARGE ACCESS TIME TIME (See Note 1) (See Note 1) (See Note 1) ADDRESS tOVDREG tOHDREG tOVCEx tOHCEx tOVPCD DATA tOVD tOHD tOVWE ...
Page 47
... MMC command or data Read and Write. SOC OUTPUT Figure 31. MMC Command/Data Read and Write Timing ACBITCLK ACOUT/ACSYNC ACIN Preliminary data sheet NXP Semiconductors AC97 Interface Waveform Figure 32 shows the waveforms and timing for the AC97 interface Data Setup and Hold. MMC CLOCK tIS tIH ...
Page 48
... ACSYNC/ACOUT ACBITCLK ACSYNC BIT ACIN/ACOUT LCDDCLK LCDVD (SoC Output) 48 NXP Semiconductors Color LCD Controller Waveforms Figure 35 shows the Valid Output Setup Time for LCD data. Timing diagrams for each CLCDC mode appear in Figure 36 through Figure 41. tOS ACIN Figure 33. ACI Signal Timing 7 ...
Page 49
... System-on-Chip Figure 36. STN Horizontal Timing Diagram Preliminary data sheet NXP Semiconductors Rev. 01 — 16 July 2007 LH7A400 49 ...
Page 50
... LH7A400 50 NXP Semiconductors Figure 37. STN Vertical Timing Diagram Rev. 01 — 16 July 2007 32-Bit System-on-Chip Preliminary data sheet ...
Page 51
... System-on-Chip Preliminary data sheet NXP Semiconductors Figure 38. TFT Horizontal Timing Diagram Rev. 01 — 16 July 2007 LH7A400 51 ...
Page 52
... LH7A400 52 NXP Semiconductors Figure 39. TFT Vertical Timing Diagram Rev. 01 — 16 July 2007 32-Bit System-on-Chip Preliminary data sheet ...
Page 53
... LCDCLS P2 LCDPS K6 LCDREV NOTE: Circled numbers are LHA400 pin numbers. Figure 40. AD-TFT and HR-TFT Horizontal Timing Diagram Preliminary data sheet NXP Semiconductors 1 AD-TFT or HR-TFT HORIZONTAL LINE TIMING0:HSW 001 002 003 004 005 006 007 008 PIXEL DATA TIMING0:HSW + TIMING0:HBP 001 002 003 004 005 006 ...
Page 54
... Oscillator Stabilization Time after Power On* tOSC14 14.7456 MHz Oscillator Stabilization Time after Wake UP tURESET/tPWRFL nURESET/nPWRFL Pulse Width NOTE: *VDDC = VDDCmin 54 NXP Semiconductors TIMING1:VSW 1.5 µ µs 2x H-LINE ‘battery good’ indication caused by alkaline battery recovery that can immediately follow a battery-low switch off ...
Page 55
... WAKEUP XTAL14 nPOR nURESET nPWRFL nPOR 2 sec. WAKEUP (asynchronous) CLKEN HCLK Preliminary data sheet NXP Semiconductors tOSC14 Figure 42. Oscillator Start-up tURESET tPWRFL Figure 43. External Reset ≤ 7.8125 ms 7.8125 ms START UP Figure 44. Signal Timing After Reset Rev. 01 — 16 July 2007 LH7A400 LH7A400-25 ...
Page 56
... R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1 ≤ 5%. Figure 45. 32.768 kHz External Oscillator Components and Schematic 56 NXP Semiconductors ENABLE XTALIN XTALOUT Y1 32.768 kHz R1 18 MΩ ...
Page 57
... R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1 ≤ 5%. Figure 46. 14.7456 MHz External Oscillator Components and Schematic Preliminary data sheet NXP Semiconductors ENABLE XTALIN Y1 14.7456 MHz R1 1 MΩ ...
Page 58
... The low-pass filter prevents high frequency noise from adversely affecting the PLL circuits. The distance from the IC pin to the high fre- quency capacitor should be as short as possible. 58 NXP Semiconductors VDDC (SOURCE) 10 µH 22 µF Figure 47. VDDA, VSSA Filter Circuit ...
Page 59
... ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.5 1.45 0.55 17.2 mm 1.95 0.3 1.25 0.45 16.8 OUTLINE VERSION IEC SOT1018-1 Figure 48. Package outline SOT1018-1 (BGA256) Preliminary data sheet NXP Semiconductors ∅ 1/2 e ∅ 1 scale 15.75 17.2 15 ...
Page 60
... ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 1.35 0.5 14.1 mm 1.7 0.3 1.15 13.9 0.4 OUTLINE VERSION IEC SOT1020-1 Figure 49. Package outline SOT1020-1 (LFBGA256) 60 NXP Semiconductors ∅ 1/2 e ∅ 1 scale 14.1 0 0.15 0.08 13.9 REFERENCES ...
Page 61
... Release date Data sheet status LH7A400_N_1 20070716 Preliminary data sheet Modifications: • First NXP version based on the LH7A400 data sheet of 20070509 Preliminary data sheet NXP Semiconductors Table 14. Revision history Change notice Supersedes - FAST LH7A400 v1-5 5-9-07 Rev. 01 — 16 July 2007 LH7A400 ...
Page 62
... NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. ...
Page 63
... Dear customer from June 1 , 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. ...
Page 64
... Terms and conditions of sale (DS) Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors ...
Page 65
... The product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage ...