LH79520N0M000B1 NXP Semiconductors, LH79520N0M000B1 Datasheet

LH79520N0M000B1

Manufacturer Part Number
LH79520N0M000B1
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of LH79520N0M000B1

Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Processing Unit
Microcontroller
Operating Supply Voltage (min)
1.62V
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
1.98V
Package Type
LQFP
Screening Level
Industrial
Pin Count
176
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LH79520N0M000B1
Manufacturer:
Sharp Microelectronics
Quantity:
10 000
FEATURES
Preliminary data sheet
• Highly Integrated System-on-Chip
• High Performance (77.4144 MHz CPU Speed)
• ARM720T™ RISC Core
• 32 kB On-Chip SRAM
• Flexible, Programmable Memory Interface
• Multi-stream DMA Controller
• Clock and Power Management
• Low Power Modes
• Watchdog Timer
• Vectored Interrupt Controller
• Three UARTs
• Two 16-bit Pulse Width Modulators
• Two Dual Channel Timer Modules
• Real Time Clock
Preliminary data sheet
– 32-bit ARM7TDMI™ RISC Core
– 8 kB Cache
– MMU (Windows CE™ Enabled)
– Write Buffer
– SDRAM Interface
– SRAM/Flash/ROM Interface
– Four 32-bit Burst-based Data Streams
– 32.768 kHz Oscillator for Real Time Clock
– 14.7456 MHz Oscillator and On-chip PLL for
– Active, Standby, Sleep and Stop Power Modes
– Externally-supplied Clock Options
– Active Mode: 55 mA (MAX.)
– Standby Mode: 35 mA (MAX.)
– Sleep Mode: 5.5 mA (MAX.)
– Stop Mode 2: 18 µA
– 16 Standard and 16 Vectored IRQ Interrupts
– Hardware Interrupt Priority
– Software Interrupts
– FIQ Fast Interrupts
– 16-byte FIFOs for Rx and Tx
– IrDA SIR Support
– Supports Data Rates Up to 460.8 kb/s
– 32-bit Up-counter with Programmable Load
– Programmable 32-bit Match Compare Register
– 15-bit External Address Bus
– 32-bit External Data Bus
– Two Segments (128 MB each)
– 26-bit External Address Bus
– 32-bit External Data Bus
– Seven Segments (64 MB Each)
CPU and Bus Clocks
• 64 Programmable General Purpose I/O Signals
• Programmable Color LCD Controller
• Synchronous Serial Port
• JTAG Debug Interface and Boundary Scan
• 5 V Tolerant Digital I/O
DESCRIPTION
plete System-on-Chip with a high level of integration to
satisfy a wide range of requirements and expectations.
The LH79520 combines a 32-bit ARM720T RISC,
Color LCD controller, Cache, Local SRAM, a number of
essential peripherals such as Direct Memory Access,
Serial and Parallel Interfaces, Infrared support, Timers,
Real Time Clock, Watchdog Timer, Pulse Width Modu-
lators, and an on-chip Phase Lock Loop. Debug is
made simple by JTAG support.
costs, reduces development cycle time and acceler-
ates product introduction. The LH79520’s fully static
design, power management unit, low voltage operation
(1.8 V Core, 3.3 V I/O), on-chip PLL, fast interrupt
response time, on-chip cache and SRAM, powerful
instruction set, and low power RISC core provide high
performance.
cessing capability is required. This capability must come
with increased performance in the display system and
peripherals, and yet demand less power from batteries.
The LH79520 is an integrated solution to fit these needs.
– Multiplexed with Peripheral I/O Signals
– Up to 800 × 600 Resolution
– Supports STN, Color STN, AD-TFT, TFT
– Supports 15 Shades of Gray
– TFT: Supports 64 k Direct Colors or 256 Colors
– Color STN: Supports 3,375 Direct Colors or 256
– Supports Data Rates Up to 1.8452 Mb/s
– Compatible with Common Interface Schemes
– XTALIN and XTAL32IN inputs are 1.8 V ± 10 %
The LH79520, powered by an ARM720T, is a com-
This high level of integration lowers overall system
To build an advanced portable device, advanced pro-
selected from a Palette of 64,000 Colors
Colors Selected from a Palette of 3,375 Colors
– Motorola SPI™
– National Semiconductor MICROWIRE™
– Texas Instruments SSI
System-on-Chip
LH79520
1

Related parts for LH79520N0M000B1

LH79520N0M000B1 Summary of contents

Page 1

Preliminary data sheet FEATURES • Highly Integrated System-on-Chip • High Performance (77.4144 MHz CPU Speed) • ARM720T™ RISC Core – 32-bit ARM7TDMI™ RISC Core – Cache – MMU (Windows CE™ Enabled) – Write Buffer • On-Chip ...

Page 2

... LH79520 ORDERING INFORMATION Type number Name LH79520N0Q000B1 LQFP176 2 NXP Semiconductors Table 1. Ordering information Package Description plastic low profile quad flat package; 176 leads; body 1.4 mm Rev. 01 — 16 July 2007 System-on-Chip Version SOT1017-1 Preliminary data sheet ...

Page 3

... System-on-Chip DEBUG/TEST INTERFACE RESET TEST LOGIC / PIN ARM 720T MUXING CONTROLLER EXTERNAL BUS INTERFACE CONTROLLER Preliminary data sheet NXP Semiconductors EXTERNAL 14.7456 MHz 32.768 kHz INTERRUPTS OSCILLATOR, PLL POWER MANAGEMENT, and RESET CONTROL 32KB SRAM CONDITIONED EXTERNAL INTERRUPTS VECTORED INTERRUPT CONTROLLER ...

Page 4

... LH79520 PIN CONFIGURATION 4 NXP Semiconductors 1 132 LH79520 44 89 002aad212 Figure 2. LH79520 pin configuration Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...

Page 5

... DEOT1 Output 145 DACK1 Output 144 DREQ1 Input Preliminary data sheet NXP Semiconductors Table 2. LH79520 Signal Descriptions DESCRIPTION MEMORY INTERFACE (MI) Address Signals Data Input/Output Signals SDRAM Clock Data Mask Output to SDRAMs Data Mask Output to SDRAMs Data Mask Output to SDRAMs Data Mask Output to SDRAMs ...

Page 6

... UARTTX0 Output 163 UARTIRRX0 Input 162 UARTIRTX0 Output 6 NXP Semiconductors DESCRIPTION COLOR LCD CONTROLLER (CLCDC) LCD Panel Data bus LCD Data Enable Frame Pulse (STN), Vertical Synchronization Pulse (TFT) Line Synchronization Pulse (STN), Horizontal Synchronization Pulse (TFT) LCD Panel Data Clock ...

Page 7

... PF3 67 PF2 99 PF1 101 PF0 Preliminary data sheet NXP Semiconductors DESCRIPTION UART1 (U1) UART1 Received Serial Data Input UART1 Transmitted Serial Data Output UART2 (U2) UART2 Received Serial Data Input UART2 Transmitted Serial Data Output GENERAL PURPOSE INPUT/OUTPUT (GPIO) General Purpose I/O Signals - Port A ...

Page 8

... Output 175 TEST1 Input 176 TEST2 Input 1 nTSTA Input 8 NXP Semiconductors DESCRIPTION General Purpose I/O Signals - Port G General Purpose I/O Signals - Port H COUNTER/TIMER (C/T) Counter/Timer Output Reset Input Reset Output External Interrupt Input External Interrupt Input External Interrupt Input External Interrupt Input ...

Page 9

... Immediately after reset, pin 144 can be programmed to function as INT5, DREQ1 or both. Software should avoid enabling both of these functions simultaneously. Pin 144 can also be programmed to function as nWAIT, rendering the INT5/DREQ1 choice unavailable. Preliminary data sheet NXP Semiconductors DESCRIPTION POWER AND GROUND (GND) Core Power Supply ...

Page 10

... VDD VSS 34 PH7 nBLE3 35 PH6 nBLE2 36 nBLE1 37 nBLE0 38 nOE 10 NXP Semiconductors OUTPUT 5 TYPE 7 DRIVE Input None Output 8 mA Output 8 mA Output 8 mA Output 8 mA Output 8 mA Output 8 mA Power None Output 8 mA Output 8 mA Output 8 mA Output 8 mA Ground None Output ...

Page 11

... VDD 65 PF4 D18 66 PF3 D17 67 PF2 D16 68 D15 69 D14 70 VSS 71 D13 72 D12 73 D11 74 D10 75 VDDC Preliminary data sheet NXP Semiconductors OUTPUT 5 TYPE 7 DRIVE Output 8 mA Power None Ground None Output 8 mA Output 8 mA Output 8 mA Power None I I I/O ...

Page 12

... PE4 nSDWE 107 nRAS 108 nCAS 109 PE3 110 PE2 111 PE1 112 PE0 113 VDDC 114 INT7 LCDVD11 115 INT6 LCDVD10 116 PD7 LCDVD9 12 NXP Semiconductors OUTPUT 5 TYPE 7 DRIVE I I Ground None Power None I I Input None ...

Page 13

... PB2 nDACK0 148 PB1 DEOT0 149 VSS 150 INT4 PWM0 151 INT3 PWMSYNC0 152 PB0 INT2 153 PA7 INT1 154 VDDC 155 PA6 INT0 Preliminary data sheet NXP Semiconductors OUTPUT 5 TYPE 7 DRIVE I I LCDPS I Ground None Power None Output ...

Page 14

... Input with Schmitt Trigger. 5. I/O = Input/Output. 6. Software should avoid enabling the INT5 and DREQ1 functions simultaneously. 7. Output Drive Values shown are MAX. See ‘DC Specifications’. 8. Crystal Oscillator Inputs should be driven to a maximum of 1.8 V ± NXP Semiconductors OUTPUT 5 TYPE 7 DRIVE 8 mA ...

Page 15

... LCDLP LCDLP 133 LCDDCLK LCDDCLK 134 LCDDCLKIN LCDDCLKIN 135 LCDVDDEN LCDCLS 137 LCDENAB LCDSPL 142 LCDREV Preliminary data sheet NXP Semiconductors Table 4. LCD Data Multiplexing STN MONO 8-BIT COLOR SINGLE DUAL SINGLE PANEL PANEL PANEL PANEL MLSTN7 CLSTN7 MLSTN6 CLSTN6 MLSTN5 ...

Page 16

... For more information, see the ARM docu- ment, ‘ARM720T (Rev 3) Technical Reference Manual’, available on NXP’s’s website at www.nxp.com. The LH79520 MMU provides a means to map Phys- ical Memory (PA) addresses to virtual memory addresses. This allows physical memory, which is con- 16 NXP Semiconductors CODEC STN/ SSP TFT/AD-TFT DMA FLASH/ ...

Page 17

... DMA Controller The DMA Controller provides support for DMA- capable peripherals. The LCD controller uses its own DMA port, connecting directly to memory for retrieving display data. Preliminary data sheet NXP Semiconductors 0xFFFFFFFF ADVANCED HIGH-PERFORMANCE BUS 0xFFFF0000 0xFFFC0000 0x80000000 0x60000000 ...

Page 18

... Row and Col- umn drivers for AD-TFT, HR-TFT, or any technology of panel that allows for a connection of this type. The 18 NXP Semiconductors Advanced LCD Interface peripheral also provides a bypass mode that allows the LH79520 to interface to the built-in timing ASIC in standard TFT and STN panels. ...

Page 19

... All of the interrupt channels, with the exception of the Watchdog Timer interrupt, can be programmed to generate: Preliminary data sheet NXP Semiconductors – FIQ interrupt request – Non-vectored IRQ interrupt request (software to poll IRQ source) – Vectored IRQ interrupt request ( chan- nels total) • ...

Page 20

... Table 7. Clock and Enable States for Different Power Modes FUNCTION 14.7456 MHz Oscillator PLL Peripheral Clock CPU Clock 20 NXP Semiconductors • Programmable clock prescalers for UARTs and PWMs • Five global power control modes are available: – Active – Standby – Sleep – ...

Page 21

... If FIQ service routine fails to clear nWDFIQ, then the next WDT time-out triggers a soft reset. Preliminary data sheet NXP Semiconductors Timer The LH79520 incorporates two Timer modules, each comprising two 16-bit independently programma- ble timers. This gives a total of four independent timers. ...

Page 22

... NOTES: 1. Core Voltage should never exceed I/O Voltage after initial power up. See the section titled ‘Power Supply Sequencing’. 2. Using 14.7456 MHz Input Crystal and On-Chip PLL. Functional to DC when using external clock. 22 NXP Semiconductors SYMBOL RATING UNIT VDDC -0 ...

Page 23

... Current measured with CPU stopped and all peripherals enabled. AC Test Conditions PARAMETER Supply Voltage (VDD) Core Voltage (VDDC) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Ref. Levels Preliminary data sheet NXP Semiconductors MIN. TYP. MAX. UNIT 2.0 5.5 0.8 1.60 1.20 0.40 2.6 2 ...

Page 24

... CLOCK OUTPUT SIGNAL (O) INPUT SIGNAL (I) 24 NXP Semiconductors For outputs from the LH79520, tOVXXX (e.g. tOVA) represents the amount of time for the output to become valid from the rising edge of the reference clock signal. Maximum requirements for tOVXXX are shown in Table 8. The signal tOHXXX (e.g. tOHA) represents the amount of time the output will be held valid from the ris- ing edge of the reference clock signal ...

Page 25

... Output SDCKE Output DQM[3:0] Output nSDCS[1:0] Output SDCLK Output Preliminary data sheet NXP Semiconductors SYMBOL MIN. tOVD tHCLK + 6 ns tOHD 3 × tHCLK - × tHCLK – tIDD 2 × tHCLK – (nWAIT –1) × tHCLK tOVCS tHCLK + 6 ns tOHCS 3 × tHCLK - 6 ns ...

Page 26

... INTR[5:0] are asynchronous signals. Interrupts must be held Active until serviced in Level Sensitive Mode, and held Active for a minimum Edge Sensitive Mode. 2. nDACK0, DACK1 and DREQ[1:0] are asynchronous signals. They must be held Active until serviced, for a minimum of 20 ns. 26 NXP Semiconductors SYMBOL MIN. SYNCHRONOUS SERIAL PORT (SSP) tOVSSPFRM ...

Page 27

... Current measured with CPU stopped and all peripherals enabled. AC Test Conditions PARAMETER Supply Voltage (VDD) Core Voltage (VDDC) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Ref. Levels Preliminary data sheet NXP Semiconductors MIN. TYP. MAX. UNIT 2.0 5.5 0.8 1.60 1.20 0.40 2.6 2 ...

Page 28

... In addition to the modal current consumption, Table 10 shows the typical current consumption for each of the on-board peripheral blocks. The values were deter- mined with the peripheral clock running at maximum frequency, typical conditions, and no I/O loads. 28 NXP Semiconductors Table 9. Current Consumption by Mode SYMBOL PARAMETER ICORE Core Current ...

Page 29

... Output nRAS Output nSDWE Output SDCKE Output DQM[3:0] Output Preliminary data sheet NXP Semiconductors SYMBOL MIN. MAX. tOVD tHCLK + 6.5 ns tOHD 3 × tHCLK – × tHCLK – tIDD 2 × tHCLK – (nWAIT –1) × tHCLK tOVCS tHCLK + 6 ns tOHCS 3 × tHCLK – ...

Page 30

... UCLK LOW Time NOTES: 1. PCLK is the period chosen for the internal peripheral clock domain. 2. MAX. period is DC. See ‘Recommended Operating Conditions’. tCLKIN tCLKINL tCLKINH Figure 8. External Clock AC Timing 30 NXP Semiconductors SYMBOL MIN. tOVSC tOHSC 2 ns tSDCLK 19.37 ns SYNCHRONOUS SERIAL PORT (SSP) tOVSSPFRM ...

Page 31

... If only 2 wait states are programmed, Preliminary data sheet NXP Semiconductors then nWAIT must be asserted in the clock cycle imme- diately following the clock cycle during which the nCSx signal is asserted. Once the SMC detects that the external device has deactivated nWAIT, the SMC will complete its access in 3 system clock cycles ...

Page 32

... LH79520 32 NXP Semiconductors Figure 11. nWait Assertion Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...

Page 33

... System-on-Chip Figure 12. External Static Memory Write, One Wait State Preliminary data sheet NXP Semiconductors Rev. 01 — 16 July 2007 LH79520 33 ...

Page 34

... LH79520 Figure 13. External Static Memory Read, One Wait State 34 NXP Semiconductors Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...

Page 35

... System-on-Chip Figure 14. External Static Memory Write, Two Wait States Preliminary data sheet NXP Semiconductors Rev. 01 — 16 July 2007 LH79520 35 ...

Page 36

... LH79520 Figure 15. Synchronous Serial Port Waveform 36 NXP Semiconductors Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...

Page 37

... SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X). 2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC. Refer to the AC timing table. 3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC. 4. nDQM is LOW. Figure 17. SDRAM Bank Activate and Write Preliminary data sheet NXP Semiconductors t OHXXX READ OVXXX BANK, ...

Page 38

... NOTE: tDREQ0L = DREQ0 LOW Pulse Width = 2 HCLK MIN. tDREQ1L = DREQ1 LOW Pulse Width = 2 HCLK MIN. 38 NXP Semiconductors Figure 19 shows the timing with relation to a single read or the last word of a burst read from the requesting peripheral. Figure 20 shows the timing with relation to a single write or the last word of a burst write to the requesting peripheral ...

Page 39

... A[23:0] D[15:0] nCSx nWEN nBLE[1:0] nOE nDACK0/ DEOT0/DEOT1 DACK1 NOTE: * HCLK is an internal signal provided for reference only. Figure 20. Write, from Memory to Peripheral, Burst Size = 1 Preliminary data sheet NXP Semiconductors ADDRESS DATA ADDRESS DATA Rev. 01 — 16 July 2007 LH79520 79520-156 79520-157 39 ...

Page 40

... ADDRESS A[23:0] D[31:0] nCSx nWEN nBLE[1:0] nOE n DACK0/DEOT0/DEOT1 DACK1 NOTE: * HCLK is an internal signal, provided for reference only. Figure 21. Read, Peripheral to Memory: Peripheral Burst Size = 4 40 NXP Semiconductors DATA #1 DATA #2 DATA #3 Rev. 01 — 16 July 2007 System-on-Chip DATA #4 79520-169 Preliminary data sheet ...

Page 41

... System-on-Chip Figure 22. Write, Memory to Peripheral: Burst Size = 4; Destination Width > External Access Width Preliminary data sheet NXP Semiconductors Rev. 01 — 16 July 2007 LH79520 41 ...

Page 42

... Figure 24 presents typical vertical timing waveforms for STN panels. TFT HORIZONTAL TIMING Figure 25 presents typical horizontal timing wave- forms for TFT panels. 42 NXP Semiconductors TFT VERTICAL TIMING Figure 26 presents typical vertical timing waveforms s. for TFT panel AD-TFT AND HR-TFT HORIZONTAL TIMING ...

Page 43

... System-on-Chip Figure 23. STN Horizontal Timing Diagram Preliminary data sheet NXP Semiconductors Rev. 01 — 16 July 2007 LH79520 43 ...

Page 44

... LH79520 44 NXP Semiconductors Figure 24. STN Vertical Timing Diagram Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...

Page 45

... System-on-Chip Preliminary data sheet NXP Semiconductors Figure 25. TFT Horizontal Timing Diagram Rev. 01 — 16 July 2007 LH79520 45 ...

Page 46

... LH79520 46 NXP Semiconductors Figure 26. TFT Vertical Timing Diagram Rev. 01 — 16 July 2007 System-on-Chip Preliminary data sheet ...

Page 47

... Driver Clock) LCDVD[17:0] (LCD DATA) NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz. Figure 28. AD-TFT and HR-TFT Vertical Timing Diagram Preliminary data sheet NXP Semiconductors 1 AD-TFT or HR-TFT HORIZONTAL LINE TIMING0:HSW 001 002 003 004 005 006 007 008 PIXEL DATA ...

Page 48

... PLL to lock once XTAL is stable tRSTOH nRESETOUT hold relative to nRESETIN HIGH VDDCmin VDDC XTAL32 XTAL14 nRESETI nRESETO nRESETIN nRESETO 48 NXP Semiconductors Table 13. Reset AC Timing DESCRIPTION tOSC32 tRSTIH tOSC14 tRSTOH Figure 29. PLL Start-up tRSTIW tRSTOV Figure 30. External Reset Rev. 01 — 16 July 2007 System-on-Chip MIN ...

Page 49

... SoC. nRESETIN Figure 31. TAP Controller Reset Circuit Example Preliminary data sheet NXP Semiconductors NXP recommends that users implementing a system to meet industrial temperature standards should use an external oscillator rather than a crystal to drive the sys- tem clock input of the System-on-Chip. This change . µ ...

Page 50

... The distance from the IC pin to the high frequency capacitor must be kept as short as possible. 50 NXP Semiconductors Similarly, the VSSA path is from the IC pin to the high frequency capacitor, then to the low frequency capacitor, keeping the distance from the IC pin to the high frequency cap as short as possible ...

Page 51

... Tolerance for R1, C1 ≤ 5%. Figure 33. Suggested External Components, 32.768 kHz Oscillator (XTAL32IN and XTAL32OUT) Preliminary data sheet NXP Semiconductors Figure 34 shows the suggested external components for the 14.7456 MHz crystal circuit to be used with the NXP LH79520. The NAND gate represents the logic inside the SoC ...

Page 52

... R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1 ≤ 5%. Figure 34. Suggested External Components, 14.7456 MHz Oscillator 52 NXP Semiconductors ENABLE XTALIN XTALOUT Y1 14.7456 MHz R1 1 MΩ ...

Page 53

... H D DIMENSIONS (mm are the original dimensions) A UNIT max 0.15 1.45 0.23 mm 1.6 0.25 0.05 1.35 0.13 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT1017-1 Figure 35. Package outline SOT1017-1 (LQFP176) Preliminary data sheet NXP Semiconductors ...

Page 54

... LH79520 NOTE: Dimensions in mm. 54 NXP Semiconductors 21.25 0.4 17.2 Figure 36. Recommended PCB Footprint Rev. 01 — 16 July 2007 System-on-Chip 1.70 79520-155 Preliminary data sheet ...

Page 55

... Release date Data sheet status LH79520_N_1 20070716 Preliminary data sheet Modifications: • First NXP version based on the LH79520 data sheet of 20060330 Preliminary data sheet NXP Semiconductors Table 14. Revision history Change notice Supersedes - LH79520 Data Sheet v1_3 Rev. 01 — 16 July 2007 LH79520 ...

Page 56

... NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. ...

Page 57

... Dear customer from June 1 , 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. ...

Page 58

... Terms and conditions of sale (DS) Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors ...

Page 59

... The product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage ...

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