STPCE1HDBI STMicroelectronics, STPCE1HDBI Datasheet

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X86 Core General Purpose PC Compatible System - on - Chip POWERFUL X86 PROCESSOR 64-BIT SDRAM CONTROLLER AT 100MHz INTEGRATED PCI NORTH / SOUTH BRIDGE CONTROLLER ISA MASTER / SLAVE / DMA 16-BIT LOCAL BUS INTERFACE FOR LOW COST AND ...

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X86 Processor core Fully static 32-bit 5-stage pipeline, x86 processor fully PC compatible. Can access up to 4GB of external memory. 8KByte unified instruction and data cache with write back and write through capability. Parallel processing integral floating point unit, ...

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Programmable system activity detector Supports SMM. Supports STOPCLK. Supports IO trap & restart. Independent peripheral time-out timer to monitor hard disk, serial & parallel ports. Supports RTC, interrupts and DMAs wake-up This is preliminary information on a new product now ...

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Release 1.3 - January 29, 2002 ...

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... ISA bus) and EIDE controller. The processor bus runs at the speed of the processor (x1 mode) or half the speed (x2 mode). The STMicroelectronics x86 processor core is embedded with standard and application specific peripheral modules on the same silicon die. The core has all the functionality of the ST standard x86 processor products, including the low power System Management Mode (SMM) ...

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GENERAL DESCRIPTION - 3 power-down timers detecting system inactivity: - Doze timer (short durations). - Stand-by timer (medium durations). - Suspend timer (long durations). - House-keeping activity detection. - House-keeping timer to cope with short bursts of house-keeping activity while ...

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X86 Core Host I/F SDRAM Controller This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Figure 1-1. Functional description. ISA m/s PCI South PCI North Bridge Release 1.3 ...

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GENERAL DESCRIPTION 1.4. CLOCK TREE The STPC Elite integrates many features and generates all its clocks from a single 14MHz oscillator. This results in multiple clock domains as described in Figure 1-2. GPCLK PLL GPCLK XTALO 14.31818 MHz 8/87 This ...

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Figure 1-3. Typical ISA-based Application. Flash ISA MUX IRQ MUX DMA.REQ DMA.ACK DMUX PCI This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Super I/O RTC DMUX STPC ...

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GENERAL DESCRIPTION 10/87 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Release 1.3 - January 29, 2002 ...

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PIN DESCRIPTION 2.1. INTRODUCTION The STPC Elite integrates functionalities of the PC architecture result, many of the traditional interconnections between the host PC microprocessor and the peripheral devices are totally internal to the STPC Elite. This offers ...

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PIN DESCRIPTION Signal Name BASIC CLOCKS AND RESETS SYSRSETI# SYSRSTO# XTALI XTALO HCLK GP_CLK 1 V _xxx_PLL DD MEMORY INTERFACE MCLKI MCLKO CS#[1:0] CS#[3]/MA[13]/BA[1] CS#[2]/MA[12] MA[10:0] MD[48:10], [7:2] MD[63:49], [9:8], [1:0] RAS#[1:0] CAS#[1:0] MWE# DQM[7:0] PCI INTERFACE PCI_CLKI PCI_CLKO AD[31:0] ...

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Signal Name ISA_CLK ISA_CLK2X OSC14M LA[23:17] SA[19:0] SD[15:0] ALE MEMR#, MEMW# SMEMR#, SMEMW# IOR#, IOW# MCS16#, IOCS16# BHE# ZWS# REF# MASTER# AEN IOCHCK# IOCHRDY ISAOE# GPIOCS# IRQ_MUX[3:0] DREQ_MUX[1:0] DACK_ENC[2:0] TC RTCAS RMRTCCS# KBCS# RTCRW# RTCDS# LOCAL BUS PA[23:20], [15], [8], ...

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PIN DESCRIPTION Signal Name IDE CONTROL DA[2:0] DD[15:12] DD[11:0] PCS3#,PCS1#,SCS3#,SCS1# DIORDY PIRQ, SIRQ PDRQ, SDRQ PDACK#, SDACK# PDIOR#, SDIOR# PDIOW#, SDIOW# MISCELLANEOUS GPIO[15:0] SPKRD SCL SDA SCAN_ENABLE TCLK TDI TMS TDO 1 : These pins must be connected to the ...

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Buffer Description ANA Analog pad buffer OSCI13B Oscillator, 13 MHz, HCMOS BT8TRP_TC LVTTL Bi-Directional drive capability, Schmitt trigger BD4STRP_FT LVTTL Bi-Directional drive capability, Schmitt trigger, 5V tolerant BD4STRUP_FT LVTTL Bi-Directional drive capability, Schmitt trigger, ...

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PIN DESCRIPTION 2.2. SIGNAL DESCRIPTIONS 2.2.1. BASIC CLOCKS AND RESETS SYSRSTI# System Reset/Power good. This input is low when the reset switch is depressed. Otherwise, it reflects the power supply’s power good signal. This input is asynchronous to all clocks, ...

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These pins are inputs when a PCI master other than the STPC Elite owns the bus and outputs when the STPC Elite owns the bus. FRAME# Cycle Frame. This is the frame signal ...

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PIN DESCRIPTION when the address is below one megabyte or the cycle is a refresh cycle. SMEMW# System Memory Write. The STPC Elite generates SMEMW# signal of the ISA bus only when the address is below one megabyte. IOR# I/O ...

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RMRTCCS# ROM/Real Time clock chip select. This signal is asserted if a ROM access is decoded during a memory cycle. It should be combined with MEMR# or MEMW# signals to properly access the ROM. During a IO cycle, this signal ...

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PIN DESCRIPTION er driver. This output should be connected to 7407 type high voltage driver. SCL, SDA I²C Interface . These bidirectional pins are connected to register 22h/23h index 97h. They 2 conform electrical specifications, they have ...

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Table 2-4. ISA / IDE Dynamic Multiplexing ISA BUS (ISAOE RMRTCCS# DD[15] KBCS# DD[14] RTCRW# DD[13] RTCDS# DD[12] SA[19:8] DD[11:0] LA[23] SCS3# LA[22] SCS1# SA[21] PCS3# SA[20] PCS1# LA[19:17] DA[2:0] IOCHRDY DIORDY Signal Name BASIC CLOCKS AND ...

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PIN DESCRIPTION Signal Name ISAOE# RMRTCCS# LA[23:17] SA[19:0] SD[15:0] BHE#, MEMR# MEMW#, SMEMR#, SMEMW#, IOR#, IOW# Unknown REF# ALE, AEN DACK_ENC[2:0] TC GPIOCS# RTCDS#, RTCRW#, KBCS# RTCAS LOCAL BUS INTERFACE PA[24:0] PD[15:0] PRD# PBE#[1:0], FCS0#, FCS_0H# FCS_0L#, FCS1#, FCS_1H#, FCS_1L# ...

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Table 2-7. Pinout. Pin # Pin name AF3 SYSRSETI# AE4 SYSRSETO# A3 XTALI C4 XTALO 2 G23 HCLK H24 GP_CLK AF15 MCLKI AB23 MCLKO AE16 MA[0] AD15 MA[1] AF16 MA[2] AE17 MA[3] AD16 MA[4] AF17 MA[5] AE18 MA[6] AD17 MA[7] ...

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PIN DESCRIPTION Pin # Pin name B8 CBE[3] A8 FRAME# B7 TRDY# D8 IRDY# A7 STOP# C8 DEVSEL# B6 PAR D7 SERR# A6 LOCK# D20 PCI_REQ#[0] C21 PCI_REQ#[1] A21 PCI_REQ#[2] C22 PCI_GNT#[0] A22 PCI_GNT#[1] B21 PCI_GNT#[2] A5 PCI_INT[0] C6 PCI_INT[1] ...

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Pin # Pin name 1 G24 VDD_CPUCLK_PLL 1 F25 VDD_DEVCLK_PLL 1 AC17 VDD_MCLKI_PLL 1 AC15 VDD_MCLKO_PLL 1 F26 VDD_HCLK_PLL 1 D11 VDD_CORE 1 L23 VDD_CORE 1 T4 VDD_CORE 1 AC6 VDD_CORE D6 VDD D16 VDD D21 VDD F4 VDD F23 ...

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PIN DESCRIPTION 26/87 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Release 1.3 - January 29, 2002 ...

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STRAP OPTION This chapter defines the STPC Elite Strap Options and their location. Some strap options have been left programmable for future versions of silicon.. Signal MD2 MD3 MD4 MD5 MCLK/HCLK Sync (see MD6 MD7 MD10 MD11 MD16 MD17 ...

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STRAP OPTION 3.1. POWER ON STRAP REGISTER DESCRIPTIONS 3.1.1. STRAP REGISTER 0 CONFIGURATION Strap0 7 6 MD7 MD6 This register defaults to the values sampled on MD[7:0] pins after reset Bit Number Sampled Mnemonic Bits 7-6 MD[7:6] Bit 5 MD5 ...

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STRAP REGISTER 1 CONFIGURATION Strap1 7 6 Rsv This register defaults to the values sampled on MD[11:10] pins after reset Bit Number Sampled Mnemonic Bits 7-6 Rsv Bits 5-4 Rsv Bit 3 MD11 Bit 2 MD10 Bits 1-0 Rsv ...

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STRAP OPTION 3.1.3. STRAP REGISTER 2 CONFIGURATION Strap2 7 6 Rsv This register defaults to the values sampled on MD[23] and MD[19:16] pins after reset Bit Number Sampled Mnemonic Bits 7-6 Rsv Bit 5 MD23 Bit 4 Rsv Bit 3 ...

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HCLK STRAP REGISTER CONFIGURATION HCLK_Strap 7 6 MD3 MD2 This register defaults to the values sampled on MD[3:2] and MD[26:24] pins after reset Bit Number Sampled Mnemonic Bits 7-3 MD[3:2] & [26:24] Bits 2-0 Rsv Bit 7 Bit 6 ...

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STRAP OPTION 32/87 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Release 1.3 - January 29, 2002 ...

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ELECTRICAL SPECIFICATIONS 4.1. INTRODUCTION The electrical specifications in this chapter are valid for the STPC Elite. 4.2. ELECTRICAL CONNECTIONS 4.2.1. POWER/GROUND DECOUPLING Due to the high frequency of operation of the STPC Elite necessary to install and ...

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ELECTRICAL SPECIFICATIONS 4.4. DC CHARACTERISTICS Symbol Parameter V 3.3V Operating Voltage DD V 2.5V Operating Voltage CORE P 3.3V Supply Power DD P 2.5V Supply Power CORE V Input Low Voltage IL V Input High Voltage IH I Input Leakage ...

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Table 4-4. 2.5V Power Consumptions (V HCLK CPUCLK (MHz) (MHz (x1) 100 100 (x1) 66 133 (x2) 66 133 (x2) Note 1: PCI clock at 33MHz Table 4-5. 3.3V Power Consumptions (V HCLK CPUCLK (MHz) (MHz ...

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ELECTRICAL SPECIFICATIONS 4.5. AC CHARACTERISTICS This section lists the AC characteristics of the STPC interfaces including output delays, input setup requirements, input hold requirements and output float delays. These measurements are based on the measurement points identified in Figure 4-1 ...

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Figure 4-2. CLK Timing Measurement Points (MIN) V Ref V IL (MAX) CLK One Clock Cycle LEGEND Minimum Time Minimum Time Clock Fall Time ...

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ELECTRICAL SPECIFICATIONS 4.5.1. POWER ON SEQUENCE Figure 4-3 describes the power-on sequence of the STPC, also called cold reset. There is no dependency between the different power supplies and there is no constraint on their rising time. SYSRSTI ...

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RESET SEQUENCE Figure 4-4 describes the reset sequence of the STPC, also called warm reset. The constraints on the strap options and the bus activities are the same as for the cold reset. The SYSRSTI# pulse duration must be ...

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ELECTRICAL SPECIFICATIONS 4.5.3. SDRAM INTERFACE Figure 4-5 and Table 4-8 list the AC characteris- tics of the SDRAM interface. The MCLKx clocks are the input clock of the SDRAM devices MCLKx T delay MCLKI STPC.output STPC.input T hold Table 4-8. ...

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PCI INTERFACE Table 4-9 lists the AC characteristics of the PCI in- terface. Table 4-9. PCI Bus AC Timing Name Parameter PCI_CLKI to AD[31:0] valid PCI_CLKI to FRAME valid PCI_CLKI to CBE[3:0] valid PCI_CLKI to PAR valid PCI_CLKI to ...

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ELECTRICAL SPECIFICATIONS 4.5.5 IPC INTERFACE Table 4-10 lists the AC characteristics of the IPC interface. ISACLK2X ISACLK IRQ_MUX[3:0] DREQ_MUX[1:0] Name Parameter T ISACLK2X to ISACLK delay dly ISACLK2X to DACK_ENC[2:0] valid ISACLK2X to TC valid T IRQ_MUX[3:0] Input setup to ...

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ISA INTERFACE AC TIMING CHARACTERISTICS Table 4-7 and Table 4-11 list the AC characteris- tics of the ISA interface. Table Figure 4-7 ISA Cycle (ref ALE AEN LA [23:17] Valid Address SA [19:0] CONTROL (Note 1) IOCS16# MCS16# IOCHRDY ...

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ELECTRICAL SPECIFICATIONS Name Parameter 10d Memory access to 8-bit ISA Slave 10e SA[19:0] & SBHE valid before IOR#, IOW# asserted 11 ISACLK2X to IOW# valid 11a Memory access to 16-bit ISA Slave - 2BCLK 11b Memory access to 16-bit ISA ...

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Name Parameter 24 IOR#, IOW# asserted before SA[19:0] 24o I/O access to 16-bit ISA Slave Standard cycle 24r I/O access to 16-bit ISA Slave Standard cycle 25 MEMR#, MEMW# asserted before next ALE# asserted 25b Memory access to 16-bit ISA ...

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ELECTRICAL SPECIFICATIONS Name Parameter 41 SA[19:0] SBHE valid to IOCHRDY negated 41a Memory access to 16-bit ISA Slave 41b Memory access to 8-bit ISA Slave 41c I/O access to 16-bit ISA Slave 41d I/O access to 8-bit ISA Slave 42 ...

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Name Parameter 64e IOW# negated to write data invalid MEMW# negated to copy data float, 8-bit ISA Slave, odd Byte 64f by ISA Master IOW# negated to copy data float, 8-bit ISA Slave, odd Byte by 64g ISA Master Note: ...

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ELECTRICAL SPECIFICATIONS 4.5.7 LOCAL BUS INTERFACE Figure 4-3 to Figure 4-11 and AC characteristics of the Local Bus interface. HCLK PA[ ] bus T setup CSx# PRD#[1:0] PD[15:0] HCLK PA[ ] bus T setup CSx# PRD#[1:0] PD[15:0] PRDY 48/87 This ...

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Figure 4-10. Synchronous Write Cycle HCLK PA[ ] bus T setup CSx# PWR#[1:0] PD[15:0] Figure 4-11. Asynchronous Write Cycle HCLK PA[ ] bus T setup CSx# PWR#[1:0] PD[15:0] PRDY This is preliminary information on a new product now in development ...

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ELECTRICAL SPECIFICATIONS The Table 4-12 below refers to Vh, Va, Vs which are the register value for Setup time, Active Time Cycle Memory (FCSx#) Peripheral (IOCSx#) Table 4-13. Local Bus Interface AC Timing Name Parameters HCLK to PA bus HCLK ...

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IDE INTERFACE Table 4-14 lists the AC characteristics of the IDE interface. Name Parameters DD[15:0] setup to PIOR#/SIOR# falling DD[15:0} hold to PIOR#/SIOR# falling This is preliminary information on a new product now in development or undergoing evaluation. Details ...

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ELECTRICAL SPECIFICATIONS 4.5.9 JTAG INTERFACE Figure 4-12 and Table 4-15 characteristics of the JTAG interface. T reset TRST TCK TMS,TDI TDO STPC.input STPC.output Name Parameter Treset TRST pulse width Tcycle TCLK period TCLK rising time TCLK falling time Tjset TMS ...

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MECHANICAL DATA 5.1. 388-PIN PACKAGE DIMENSION The pin numbering for the STPC 388-pin Plastic BGA package is shown in Figure Figure 5-1. 388-Pin PBGA Package - Top View ...

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MECHANICAL DATA Figure 5-2. 388-pin PBGA Package - PCB Dimensions A1 Ball Pad Corner A Table 5-1. 388-pin PBGA Package - PCB Dimensions Symbols Min A 34.95 B 1.22 C 0.58 D 1.57 E 0.15 F 0.05 G 0.75 54/87 ...

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Figure 5-3. 388-pin PBGA Package - Dimensions C Solderball A Table 5-2. 388-pin PBGA Package - Dimensions Symbols Min A 0.50 B 1.12 C 0.60 D 0.52 E 0. Solderball after collapse G mm Typ ...

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MECHANICAL DATA 5.2. 388-PIN PACKAGE THERMAL DATA The 388-pin PBGA package has a Power Dissipation Capability of 4.5W. This increases to 6W when used with a Heatsink. Signal layers Figure 5-5. Thermal Dissipation Without Heatsink Board Ambient Rca Case Rjc ...

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Figure 5-6. Thermal Dissipation With Heatsink Board Ambient Rca Case Rjc Board Junction 8.5 Rjb Board Rba Ambient Rja = 9.5 °C/W Board dimensions: Junction - 10 12 layers (2 for signals, 1 GND, 1VCC) ...

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MECHANICAL DATA 5.3. SOLDERING RECOMMENDATIONS High quality, low defect soldering requires identifying the optimum temperature profile for reflowing the solder paste, therefore optimizing the process. The heating and cooling rise rates must be compatible with the solder paste and components. ...

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DESIGN GUIDELINES 6.1. TYPICAL APPLICATIONS The STPC Elite is well suited for many display- less applications or together with a PCI graphics/ video device. Some of implementations are described below. This is preliminary information on a new product now ...

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DESIGN GUIDELINES 6.2. STPC CONFIGURATION The STPC is a very flexible product thanks to decoupled clock domains and to strap options enabling a user-optimized configuration. As some trade off are often necessary important analysis of ...

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ARCHITECTURE RECOMMENDATIONS This section describes implementations for the STPC interfaces. For more details, download Schematics from the STPC web site. 6.3.1. POWER DECOUPLING An appropriate decoupling of the various STPC power pins is mandatory for optimum behaviour. When insufficient, ...

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DESIGN GUIDELINES 6.3.3. SDRAM The STPC provides all the signals for SDRAM control 128 MBytes of main memory are supported. All Banks must be 64 bits wide memory banks are available when using 16Mbit devices. ...

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Figure 6-5. One Memory Banks with 8 Chips (8-bit) MCLKI 10pF MCLKO CY2305 CS0# MA[12:0] BA[1:0] RAS0# CAS0# WE# DQM[7:0] MD[63:0] Figure 6-6. Two Memory Banks with 8 Chips (8-bit) MCLKI 22pF MCLKO CY2305 CS1# CS0# MA[12:0] BA[1:0] RAS0# CAS0# ...

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DESIGN GUIDELINES For other implementations like 32-bit SDRAM devices, refers to the SDRAM controller signal SDRAM Density Internal Banks DIMM Pin Number ... 123 126 39 122 BA0 (MA11) Address Mapping: 16 Mbit - 2 internal banks STPC I/F BA0 ...

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PCI BUS The PCI bus is always active and the following control signals must be pulled- through 2K2 resistors even if this bus is not connected to an external device: FRAME#, TRDY#, IRDY#, STOP#, DEVSEL#, ...

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DESIGN GUIDELINES 6.3.5. LOCAL BUS The local bus has all the signals to connect flash devices or I/O devices with the minimum glue logic. Figure 6-9. Typical 16-bit boot flash implementation 22 PA[22:1] FCS0# PRD0# PRD1# PWR0# PWR1# 16 PD[15:0] ...

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IPC Most of the IPC signals are multiplexed: Interrupt inputs, DMA Request inputs, DMA Acknowledge outputs. The figure below describes a complete implementation of the IRQ[15:0] time-multiplexing. Timer 0 Keyboard Slave PIC COM2/COM4 COM1/COM3 LPT2 Floppy LPT1 RTC Mouse ...

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DESIGN GUIDELINES The figure below describes implementation of the external glue logic for DMA Request time-multiplexing and DMA Acknowledge demultiplexing. Like for the interrupt lines, this Figure 6-11. Typical DMA multiplexing and demultiplexing ISA, Refresh ISA, PIO ISA, FDC ISA, ...

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IDE / ISA DYNAMIC DEMULTIPLEXING Some of the ISA bus signals are dynamically multiplexed to optimize the pin count. Figure 6-12. Typical IDE / ISA Demultiplexing STPC bus / DD[15:0] 6.3.8. BASIC AUDIO USING IDE INTERFACE When the application ...

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DESIGN GUIDELINES 6.3.9. JTAG INTERFACE The STPC integrates a JTAG interface for scan- chain and on-board testing. The only external Figure 6-14. Typical JTAG implementation TCLK TDO TMS TDI TRST STPC 70/87 This is preliminary information on a new product ...

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PLACE AND ROUTE RECOMMENDATIONS 6.4.1. GENERAL RECOMMENDATIONS Some STPC Interfaces run at high speed and need to be carefully routed or even shielded like: 1) Memory Interface 2) PCI bus 3) 14 MHz oscillator stage ground pad This is ...

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DESIGN GUIDELINES 6.4.2. MEMORY INTERFACE 6.4.2.1. Introduction In order to achieve SDRAM memory interfaces which work at clock frequencies of 100 MHz and above, careful consideration has to be given to the timing of the interface with all the various ...

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In other words, all Low skew clock driver: MCLKO * No additional 75mm when SDRAM directly soldered ...

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DESIGN GUIDELINES The DIMM sockets should be populated starting with the furthest DIMM from the STPC device first (DIMM1). There are two types of DIMM devices; single-row and dual-row. The dual-row devices require two chip select signals to select between ...

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PCI INTERFACE 6.4.3.1. Introduction In order to achieve a PCI interface which work at clock frequencies up to consideration has to be given to the timing of the interface with all the various electrical and physical constraints taken into ...

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DESIGN GUIDELINES 6.4.3.3. Board Layout Issues The physical layout of the motherboard PCB assumed in this presentation is as shown in 6-22. For the PCI interface, the most critical signal is the clock. Any skew between the clocks at the ...

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THERMAL DISSIPATION 6.4.4.1. Power saving Thermal dissipation of the STPC depends mainly on supply voltage. When the system does not need to work at the upper voltage limit, it may therefore be beneficial to reduce the voltage to the ...

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DESIGN GUIDELINES When considering thermal dissipation, one of the most important parts of the layout is the connection between the ground balls and the ground layer. Figure 6-25. Recommended 1-wire Power/Ground Pad Layout Considering only the central matrix of 36 ...

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To avoid solder wicking over to the via pads during soldering important to have a solder mask of 4 mil around the pad (NSMD pad). This gives a diameter of 33 mil for a 25 mil ground pad. ...

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DESIGN GUIDELINES As the PCB acts as a heat sink, the layout of top and ground layers must be done with care to maximize the board surface dissipating the heat. The only limitation is the risk of losing routing channels. ...

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Figure 6-30. Recommend signal wiring (top & ground layers) with corresponding heat flow GND This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Power Power Release 1.3 - ...

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DESIGN GUIDELINES 6.5. DEBUG METHODOLOGY In order to bring a STPC-based board to life with the best efficiency recommended to follow the check-list described in this section. 6.5.1. POWER SUPPLIES In parallel with the assembly process ...

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RMRTCCS# cycle to inform the ISA controller of a 16-bit device. 6.5.3.3. POST code Once the 16 first bytes are fetched and decoded, the CPU core continue its execution depending on the content of these first data. Usually, it corresponds ...

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DESIGN GUIDELINES Check: Measure PCICLKO: - maximum is 33MHz by standard - check selected frequency 6 PCI clocks - it is generated from HCLK by a division (1/2, 1/3 or 1/4) Check PCICLKI equals PCICLKO Measure MCLKO: ...

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... ORDERING DATA 7.1. ORDERING CODES STMicroelectronics Prefix Product Family PC: PC Compatible Product ID E1: Elite Core Speed E: 100 MHz H: 133 MHz Memory Interface Speed E: 100 MHz D: 90 MHz Package B: 388 Overmoulded BGA Temperature Range C: Commercial Case Temperature (Tcase) = 0°C to +85°C I: Industrial Case Temperature (Tcase) = -40° ...

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... ORDERING DATA 7.2. AVAILABLE PART NUMBERS Core Frequency Part Number STPCE1EEBC STPCE1HDBC STPCE1EEBI STPCE1HDBI 7.3. CUSTOMER SERVICE More information is available STMicroelectronics Internet www.st.com/stpc 86/87 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. CPU Mode ...

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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...