MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1097
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
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A.2.9.2
This MPC562/MPC564 instruction is compressed into a single segment. The vocabulary table pointer
points to an offset in tables of all RAMs (DECRAMs).
The definition of the class includes:
Data brought from RAM#1 is the 16 MSBs of the decompressed instruction and data brought from
RAM#2 is the 16 LSBs of the decompressed instruction.
A.2.9.3
This MPC562/MPC564 instruction is divided into two segments. Each segment is compressed and mapped
into a different vocabulary. The vocabularies reside in different RAMs. Proper programming can swap the
vocabularies’ locations.
The definition of the class includes:
Freescale Semiconductor
MSB
MSB
•
•
•
•
Alternative #1 (CLASS_2a)
Alternative #2 (CLASS_2b)
16-bit segment #1 – to be compressed
4-bit class
4-bit class
4-bit class
TP1 length = 2-9
TP2 length = 0
TP1 base address, TP2 base address = the two tables’ base addresses for RAM #1 and RAM #2,
respectively.
AS, DS=0
Single Segment Full Compression – CLASS_1
Twin Segment Full Compression – CLASS_2
2- to 9-bit TP1 for segment #1
2- to 9-bit TP1 for segment #2
32-bit segment – to be compressed
2-to 9-bit TP1
Figure A-7. CLASS_1 Instruction Layout
Figure A-8. CLASS_2 Instruction Layout
MPC561/MPC563 Reference Manual, Rev. 1.2
Uncompressed Instruction
Uncompressed Instruction
Compressed Instruction
Compressed Instruction
16-bit segment #2 – to be compressed
2- to 9-bit TP2 for segment #2
2- to 9-bit TP2 for segment #1
MPC562/MPC564 Compression Features
A-9
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