MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 1404
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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CR0 field 3-17
CR1 field 3-17
CRAM_OTR register 22-18
CRAM_OVLCR register 22-17
CRAM_RBAx register 22-16
CRAMMCR register 22-13
CRCERR 16-34
CRWE 23-47
CRWF 23-47
CSG 23-48
CSH 23-48
CTA 23-51
CTB 23-51
CTC 23-51
CTD 23-51
CTE 23-47
CTF 23-47
CTG 23-47
CTH 23-47
CTR 3-5
CWP 13-24
Cyclic redundancy check error (CRCERR) 16-34
D
DAC 13-2
DAE/source instruction service register 3-22
DAR 3-23
DAR, 3-48
Data
DATA [0:31] 9-6
Data address register 3-23
data memory protection unit 11-1
data reservation 11-7
data storage interrupt, 3-48
DC 24-10
DCCR 4-25
DCCR0-15 A-19
DDRQS 15-10
Debug enable register 23-53
debug mode 23-21
DEC 3-23
DECE 23-42
DECEE 23-44
decompression
Decrementer
decrementer 6-18
Decrementer exception 3-53
deep-sleep 6-23
Index-4
frame 15-52
features A-1
modes of A-14
register 3-23
,
,
,
,
,
,
,
6-18
,
14-2
3-48
,
3-59
A-17
A-17
A-17
A-17
13-27
,
,
15-34
,
6-40
3-59
,
14-25
,
15-39
,
14-28
MPC561/MPC563 Reference Manual, Rev. 1.2
Delay
DER 23-43
Development Port
development port 23-28
development support
DID 24-9
Digital
DIO D-46
Disable TPU2 pins field (DTPU) 19-20
Disabled mode 13-41
Discrete input/output (DIO) D-46
DIV2 19-19
DIV8 clock 19-7
Divide by two control field (DIV2) 19-19
DIW0EN 23-52
DIW1EN 23-52
DIW2EN 23-52
DIW3EN 23-52
DLW0EN 23-50
DLW1EN 23-50
DMBR register 10-36
DMOR register 10-37
DMPU 11-1
Double
doze 6-23
DPI 23-43
DPTMCR 20-3
DPTRAM 20-4
DPTRAM operation 20-6
DSCK 15-24
DSCKL 15-19
DSCR 19-12
DSISR 3-22
DSSR 19-13
DT 15-24
after transfer (DT) 15-24
before SCK (DSCKL) 15-19
trap enable selection 23-52
debug mode 23-21
instruction support 23-14
port registers 23-30
program trace 23-4
protection features 23-40
registers 23-39
system interface 23-19
watchpoints 23-9
control section
input/output port (PQA) 13-66
to analog converter (DAC) 13-2
-buffered 15-54
contents 13-2
14-38
,
,
23-53
3-48
–??
,
,
,
,
A-17
A-17
A-17
A-17
, ??–
,
,
15-57
3-50
,
13-34
14-42
,
3-59
,
,
15-36
,
13-37
A-17
Freescale Semiconductor
,
14-65
,
–??,
13-36
14-2
,
14-2
, ??–
,
14-35
14-37
,
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