MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 383
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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The MPC561/MPC563 samples the CR line at the rising edge of CLKOUT. When this signal is asserted,
the reservation flag is reset (negated).
The external bus interface (EBI) samples the logical value of the reservation flag prior to externally
starting a bus cycle initiated by the RCPU stwcx instruction. If the reservation flag is set, the EBI begins
with the bus cycle. If the reservation flag is reset, no bus cycle is initiated externally, and this situation is
reported to the RCPU.
The reservation protocol for a multi-level (local) bus is illustrated in
situation in which the reserved location is sited in the remote bus.
Freescale Semiconductor
lwarx
MPC500 Device
External Bus
CLKOUT
S
R
Interface
Q
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 9-30. Reservation on Local Bus
AT[0:3], RSV, R/W, TS
CR
External Bus
Reservation
Logic
ADDR[0:29]
Figure
9-31. The system describes the
CR
External Bus Interface
Master
Bus
9-43
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