MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 387
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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When the MPC561/MPC563 initiates a burst access, the bus interface recognizes the RETRY assertion as
a retry termination only if it detects it before the first data beat was acknowledged by the slave device.
When the RETRY signal is asserted as a termination signal on any data beat of the access after the first
(being the first data beat acknowledged by a normal TA assertion), the MPC561/MPC563 recognizes
RETRY as a transfer error acknowledge.
Freescale Semiconductor
CLKOUT
BR (output)
BG
BB
ADDR[8:31]
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
RETRY (input)
Figure 9-33. Retry Transfer Timing – External Arbiter
MPC561/MPC563 Reference Manual, Rev. 1.2
ADDR
O
Master to Gain the Bus
Allow External
ADDR
External Bus Interface
9-47
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