MPC561MZP56 Freescale, MPC561MZP56 Datasheet - Page 967
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
Manufacturer
Freescale
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Cpu Family
MPC56x
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
56MHz
Interface Type
QSPI/SCI/SPI/UART
Total Internal Ram Size
32KB
# I/os (max)
56
Number Of Timers - General Purpose
22
Operating Supply Voltage (typ)
2.6/5V
Operating Supply Voltage (max)
2.7/5.25V
Operating Supply Voltage (min)
2.5/4.75V
On-chip Adc
2(32-chx10-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
Program Memory Type
ROMLess
Program Memory Size
Not Required
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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23.6.12 Breakpoint Address Register (BAR)
23.6.13 Development Port Data Register (DPDR)
This 32-bit special purpose register physically resides in the development port logic. It is used for data
interchange between the core and the development system. An access to this register is initiated using
mtspr and mfspr (SPR 630) and implemented using a special bus cycle on the internal bus.
Freescale Semiconductor
Reset
Field
Addr
SRESET
Serialize
Control
(SER)
Field
Addr
Bits
0:31
MSB
1
1
1
1
0
MSB
1
0
Instruction
2
(ISCTL)
1
Fetch
00
01
10
11
BARV[0:31]
Mnemonic
3
2
4
3
5
4
Illegal. This mode should not be selected.
RCPU is not serialized (normal mode) and show cycles will be performed for all changes in
the program flow
RCPU is not serialized (normal mode) and show cycles will be performed for all indirect
changes in the program flow
RCPU is not serialized (normal mode) and no show cycles will be performed for fetched
instructions
Figure 23-26. Development Port Data Register (DPDR)
6
5
Figure 23-25. Breakpoint Address Register (BAR)
6
7
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 23-27. ISCT_SER Bit Descriptions
7
8
The address of the load/store cycle that generated the breakpoint
8
Table 23-28. BAR Bit Descriptions
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Unaffected
SPR 630
Unaffected
SPR 159
Data
BARV
Functions Selected
Description
Development Support
LSB
23-53
LSB
31
31
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