MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 1327

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

0x0140–0x017F Freescale Scalable CAN — MSCAN (CAN0) Map (continued)
Freescale Semiconductor
Address
Address
0x0150–
0x0154–
0x0158–
0x0160–
0x0170–
Detailed MSCAN Foreground Receive and Transmit Buffer Layout
0xXXXB
0xXXXC
0xXXXD
0xXXXE CANxRTSRH
0xXXX0
0xXXX1
0xXXX2
0xXXX3
0xXXX4
0xXXXF
0x015C
0xXX10
0x015B
0x015F
0x016F
0x017F
0x0153
0x0157
–
–
CANxRDSR0–
CAN0IDMR0–
CAN0IDMR4–
CAN0IDAR0–
CAN0IDAR4–
CANxRDSR7
CANxRTSRL
CAN0IDMR3
CAN0IDMR7
CANxRIDR0 W
CANxRIDR1 W
CANxRIDR2 W
CANxRIDR3 W
CAN0IDAR3
CAN0IDAR7
Extended ID
Extended ID
Extended ID
Extended ID
Extended ID
CANxTIDR0
CAN0RXFG
CAN0TXFG
Standard ID
Standard ID
Standard ID
Standard ID
CANRxDLR
Standard ID
Reserved
Name
Name
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
TSR15
TSR7
Bit 7
Bit 7
ID28
ID10
ID20
ID14
ID28
ID10
AM7
AM7
DB7
AC7
AC7
ID2
ID6
(See
(See
MC9S12XDP512 Data Sheet, Rev. 2.21
TSR14
TSR6
Bit 6
Bit 6
ID27
ID19
ID13
ID27
AM6
AM6
AC6
AC6
DB6
ID9
ID1
ID5
ID9
Detailed MSCAN Foreground Receive and Transmit Buffer
Detailed MSCAN Foreground Receive and Transmit Buffer
TSR13
TSR5
Bit 5
Bit 5
ID26
ID18
ID12
ID26
AM5
AM5
AC5
AC5
DB5
ID8
ID0
ID4
ID8
FOREGROUND TRANSMIT BUFFER
FOREGROUND RECEIVE BUFFER
SRR=1
TSR12
TSR4
Bit 4
Bit 4
AM4
AM4
ID25
RTR
ID11
ID25
AC4
AC4
DB4
ID7
ID3
ID7
TSR11
IDE=1
IDE=0
DLC3
TSR3
Bit 3
Bit 3
AM3
AM3
ID24
ID10
ID24
AC3
AC3
DB3
ID6
ID2
ID6
TSR10
DLC2
TSR2
Appendix G Detailed Register Map
Bit 2
AM2
AM2
Bit 2
ID23
ID17
ID23
DB2
AC2
AC2
ID5
ID9
ID1
ID5
DLC1
TSR9
TSR1
Bit 1
Bit 1
ID22
ID16
ID22
AM1
AM1
DB1
AC1
AC1
Layout)
Layout)
ID4
ID8
ID0
ID4
DLC0
TSR8
TSR0
Bit 0
Bit 0
ID21
ID15
ID21
AM0
AM0
RTR
AC0
AC0
DB0
ID3
ID7
ID3
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