MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 430
MC9S12XDP512MAG
Manufacturer Part Number
MC9S12XDP512MAG
Description
Manufacturer
Freescale
Datasheet
1.MC9S12XDP512MAG.pdf
(1348 pages)
Specifications of MC9S12XDP512MAG
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
119
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
2(24-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in
10.3.2.5
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
430
Reset:
W
R
1
MSCAN Receiver Flag Register (CANRFLG)
WUPIF
This setting is not valid. Please refer to
TSEG13
Bit Time
1
0
7
This setting is not valid. Please refer to
0
0
0
0
1
1
:
TSEG22
0
0
1
1
:
Figure 10-8. MSCAN Receiver Flag Register (CANRFLG)
= Unimplemented
CSCIF
=
0
6
TSEG12
----------------------------------------------------- -
Prescaler value
0
0
0
0
1
1
:
f CANCLK
TSEG21
Table 10-7. Time Segment 2 Values
Table 10-8. Time Segment 1 Values
MC9S12XDP512 Data Sheet, Rev. 2.21
RSTAT1
0
0
1
1
:
0
5
TSEG11
0
0
1
1
1
1
:
Table 10-7
Table 10-35
TSEG20
RSTAT0
Table 10-35
0
4
0
1
0
1
:
1
TSEG10
+
and
TimeSegment1
0
1
0
1
0
1
:
for valid settings.
TSTAT1
Table
for valid settings.
3
0
Time Segment 2
2 Tq clock cycles
7 Tq clock cycles
8 Tq clock cycles
1 Tq clock cycle
10-8).
15 Tq clock cycles
16 Tq clock cycles
2 Tq clock cycles
3 Tq clock cycles
Time segment 1
4 Tq clock cycles
1 Tq clock cycle
TSTAT0
:
0
2
+
TimeSegment2
:
1
Freescale Semiconductor
1
OVRIF
1
1
0
1
Eqn. 10-1
RXF
0
0
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