MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 569
MC9S12XDP512MAG
Manufacturer Part Number
MC9S12XDP512MAG
Description
Manufacturer
Freescale
Datasheet
1.MC9S12XDP512MAG.pdf
(1348 pages)
Specifications of MC9S12XDP512MAG
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
119
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
2(24-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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Chapter 15
Background Debug Module (S12XBDMV2)
15.1
This section describes the functionality of the background debug module (BDM) sub-block of the
HCS12X core platform.
The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.
The BDM has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to determine the communication rate
and a handshake signal to indicate when an operation is complete. The system is backwards compatible to
the BDM of the S12 family with the following exceptions:
15.1.1
The BDM includes these distinctive features:
Freescale Semiconductor
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TAGGO command no longer supported by BDM
External instruction tagging feature now part of DBG module
BDM register map and register content extended/modified
Global page access functionality
Enabled but not active out of reset in emulation modes
CLKSW bit set out of reset in emulation mode.
Family ID readable from firmware ROM at global address 0x7FFF0F (value for HCS12X devices
is 0xC1)
Single-wire communication with host development system
Enhanced capability for allowing more flexibility in clock rates
SYNC command to determine communication rate
GO_UNTIL command
Hardware handshake protocol to increase the performance of the serial communication
Active out of reset in special single chip mode
Nine hardware commands using free cycles, if available, for minimal CPU intervention
Hardware commands not requiring active BDM
14 firmware commands execute from the standard BDM firmware lookup table
Introduction
Features
MC9S12XDP512 Data Sheet, Rev. 2.21
569
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