MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 680

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 18 Memory Mapping Control (S12XMMCV3)
18.4.3
18.4.3.1
A possible access error is flagged by the MMC and signalled to XGATE under the following conditions:
For further details refer to the XGATE Block Guide.
18.4.3.2
After programming the protection mechanism registers (see
and
module:
If the RWPE bit is set the CPU write accesses into the XGATE RAM region are blocked. If the CPU tries
to write the XGATE RAM region the AVIF bit is set and an interrupt is generated if enabled. Furthermore
if the XGATE tries to write to outside of the XGATE RAM or shared regions and the RWPE bit is set, the
write access is suppressed and the access error will be flagged to the XGATE module (see
“Illegal XGATE Accesses
The bottom address of the XGATE RAM region always starts at the lowest implemented RAM address.
The values stored in the boundary registers define the boundary addresses in 256 byte steps. The 256 byte
block selected by any of the registers is always included in the respective region. For example setting the
shared region lower boundary register (RAMSHL) to 0xC1 and the shared region upper boundary register
(RAMSHU) to 0xE0 defines the shared region from address 0x0F_C100 to address 0x0F_E0FF in the
global memory space (see
The interrupt requests generated by the MMC are listed in
for the related interrupt vector address and interrupt priority.
The following conditions must be satisfied to ensure correct operation of the RAM protection mechanism:
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1. XGATE RAM region
2. CPU RAM region
3. Shared Region (XGATE AND CPU)
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Figure
XGATE performs misaligned word (in case of load-store or opcode or vector fetch accesses).
XGATE accesses the register space (in case of opcode or vector fetch).
XGATE performs a write to Flash in any modes (in case of load-store access).
XGATE performs an access to a secured Flash in expanded modes (in case of load-store or opcode
or vector fetch accesses).
XGATE performs an access to an unimplemented area (in case of load-store or opcode or vector
fetch accesses).
XGATE performs a write to non-XGATE region in RAM (RAM protection mechanism) (in case
of load-store access).
Value stored in RAMXGU must be lower than the value stored in RAMSHL.
Value stored RAMSHL must be lower or equal than the value stored in RAMSHU.
18-20) and setting the RWPE bit (see
Chip Access Restrictions
Illegal XGATE Accesses
Illegal CPU Accesses
and the XGATE Block Guide).
Figure
18-20).
MC9S12XDP512 Data Sheet, Rev. 2.21
Figure
18-17) there are 3 regions recognized by the MMC
Table
Figure
18-22. Refer to the Device User Guide
18-17,
Figure
18-18,
Freescale Semiconductor
Section 18.4.3.1,
Figure
18-19,