MC9S12XDP512MAG Freescale, MC9S12XDP512MAG Datasheet - Page 747

• Manufacturer Part Number: MC9S12XDP512MAG
• Manufacturer: Freescale

Specifications of MC9S12XDP512MAG

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 119
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(24-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

20.3.2
This section consists of the S12XDBG control and trace buffer register descriptions in address order. Each
comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F
in the S12XDBG module register address map. When ARM is set in DBGC1, the only bits in the
S12XDBG module registers that can be written are ARM, TRIG, and COMRV[1:0]
20.3.2.1
Read: Anytime
Write: Bits 7, 1, 0 anytime, bit 6 can be written anytime but always reads back as 0.
Freescale Semiconductor
1
2
Address: 0x0020
Address
0x002C
0x002D
0x002A
0x002B
0x002E
0x002F
This represents the contents if the Comparator A or C control register is blended into this address.
This represents the contents if the Comparator B or D control register is blended into this address
Reset
W
R
Bits 5:2 anytime S12XDBG is not armed.
DBGXDHM
DBGXDLM
DBGXAM
DBGXDH
DBGXDL
DBGXAL
Register Descriptions
ARM
Name
Debug Control Register 1 (DBGC1)
0
7
When disarming the S12XDBG by clearing ARM with software, the
contents of bits[5:2] are not affected by the write, since up until the write
operation, ARM = 1 preventing these bits from being written. These bits
must be cleared using a second write if required.
W
W
W
W
W
W
R
R
R
R
R
R
TRIG
0
0
6
Bit 15
Bit 15
Bit 15
Bit 7
Figure 20-2. Quick Reference to S12XDBG Registers
Bit 7
Bit 7
Bit 7
Figure 20-3. Debug Control Register (DBGC1)
XGSBPE
MC9S12XDP512 Data Sheet, Rev. 2.21
14
14
14
0
5
6
6
6
6
13
13
13
5
5
5
5
BDM
NOTE
0
4
12
12
12
4
4
4
4
0
3
DBGBRK
11
11
11
Chapter 20 S12X Debug (S12XDBGV3) Module
3
3
3
3
0
2
10
10
10
2
2
2
2
0
1
1
9
1
9
1
9
1
COMRV
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
0
0
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