PPC405EP-3LB333C Applied Micro Circuits Corporation, PPC405EP-3LB333C Datasheet
PPC405EP-3LB333C
Specifications of PPC405EP-3LB333C
Available stocks
Related parts for PPC405EP-3LB333C
PPC405EP-3LB333C Summary of contents
Page 1
... PCI Revision 2.2 compliant interface (32-bit 66MHz) Description Designed specifically to address embedded applications, the PowerPC 405EP (PPC405EP) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-performance RISC ...
Page 2
... PPC405EP – PowerPC 405EP Embedded Processor Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PLB to PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 External Peripheral Bus Controller (EBC DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Universal Interrupt Controller (UIC 10/100 Mbps Ethernet MAC ...
Page 3
... PPC405EP – PowerPC 405EP Embedded Processor List of Figures PPC405EP Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 31mm, 385-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5V-Tolerant Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Clocking Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 List of Tables System Memory Address Map (4GB System Memory DCR Address Map ...
Page 4
... PPC405EP PPC405EP-3LB333C PPC405EP PPC405EP-3LB333CZ Notes the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray. 2. Package type G contains lead; package type L is lead-free. The part number contains a part modifier. Included in the modifier is a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only ...
Page 5
... DCU D-Cache Arb SDRAM Controller 13-bit addr 32-bit data The PPC405EP is designed using the IBM Microelectronics Blue Logic blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnect AMCC OCM Power SRAM ...
Page 6
... PPC405EP – PowerPC 405EP Embedded Processor Address Maps The PPC405EP incorporates two address maps. The first address map defines the possible use of addressable memory regions that the processor can access. The second address map defines Device Configuration Register (DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EP processor through the use of mtdcr and mfdcr instructions ...
Page 7
... PPC405EP – PowerPC 405EP Embedded Processor Table 2. DCR Address Map Function 1 Total DCR Address Space By function: Reserved Memory Controller Registers External Bus Controller Registers Reserved On-Chip Memory Controller Registers Reserved PLB Registers Reserved OPB Bridge Out Registers Reserved Clock, Control, and Reset ...
Page 8
... PPC405EP – PowerPC 405EP Embedded Processor On-Chip Memory (OCM) The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the processor core. Features include: • Low-latency access to critical instructions and data • Performance identical to cache hits without misses • ...
Page 9
... PPC405EP – PowerPC 405EP Embedded Processor SDRAM Memory Controller The PPC405EP Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to two physical banks 256MB per bank are supported maximum of 512MB. Memory timings, address and bank sizes, and memory addressing modes are programmable ...
Page 10
... PPC405EP – PowerPC 405EP Embedded Processor Serial Interface • One 8-pin UART and one 2-pin (Tx and Rx only) UART interface provided • Internal serial clock to allows a wide range of baud rates • Register compatibility with NS16750 register set • Complete status reporting capability • ...
Page 11
... PPC405EP – PowerPC 405EP Embedded Processor 10/100 Mbps Ethernet MAC • Two ports capable of handling full/half duplex 100Mbps and 10Mbps operation • Uses the medium independent interface (MII) to the physical layer (PHY not included on chip) JTAG • IEEE 1149.1 test access port • ...
Page 12
... PPC405EP – PowerPC 405EP Embedded Processor Figure 2. 31mm, 385-Ball E-PBGA Package Top View Gold Gate Release Corresponds to A01 Ball Location 15.5 TYP Notes: 1. All dimensions are in mm. 2. Package available in leaded and lead-free configurations. 0.20 Bottom View ± 31.0 0 Part Number A 31.0 27 ...
Page 13
... PPC405EP – PowerPC 405EP Embedded Processor Pin Lists The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Shared signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. Shared signals appear alphabetically multiple times in the list— ...
Page 14
... PPC405EP – PowerPC 405EP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 2 of 10) Signal Name Ball GND A01 GND A02 GND A07 GND A12 GND A17 GND A22 GND A23 GND B01 GND B02 GND B22 GND B23 GND C03 GND C21 ...
Page 15
... PPC405EP – PowerPC 405EP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 3 of 10) Signal Name Ball GND M01 GND M05 M10- GND M14 GND M19 GND M20 GND M23 N10- GND N14 P10- GND P14 GND R05 GND R19 GND U01 GND ...
Page 16
... PPC405EP – PowerPC 405EP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 4 of 10) Signal Name Ball GPIO00[PerBLast] A09 GPIO01[TS1E] AA23 GPIO02[TS2E] Y22 GPIO03[TS1O] Y23 GPIO04[TS2O] W21 GPIO05[TS3] U20 GPIO06[TS4] V23 GPIO07[TS5] U21 GPIO08[TS6] U22 GPIO09[TrcClk] T21 GPIO10[PerCS1] C02 GPIO11[PerCS2] E03 GPIO12[PerCS3] D03 ...
Page 17
... PPC405EP – PowerPC 405EP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 5 of 10) Signal Name Ball MemAddr00 AB15 MemAddr01 AB16 MemAddr02 AB17 MemAddr03 AA17 MemAddr04 AC18 MemAddr05 AA18 MemAddr06 AC19 MemAddr07 AB19 MemAddr08 Y18 MemAddr09 AA19 MemAddr10 Y19 MemAddr11 AA20 MemAddr12 AC21 ...
Page 18
... PPC405EP – PowerPC 405EP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 6 of 10) Signal Name Ball OV B11 DD OV B09 DD OV B19 DD OV C17 DD OV D13 DD OV E06 DD OV E07 DD OV E08 DD OV E16 DD OV E17 DD OV E18 DD OV E21 DD OV F05 DD OV ...
Page 19
... PPC405EP – PowerPC 405EP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 7 of 10) Signal Name Ball PCIAD00 B16 PCIAD01 C16 PCIAD02 B17 PCIAD03 D16 PCIAD04 B18 PCIAD05 D17 PCIAD06 C18 PCIAD07 A19 PCIAD08 D18 PCIAD09 C19 PCIAD10 A20 PCIAD11 B20 PCIAD12 C20 ...
Page 20
... PPC405EP – PowerPC 405EP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 8 of 10) Signal Name Ball PCIReq0/Gnt E20 PCIReq1 F20 PCIReq2 E22 PCIReset G20 PCISErr J20 PCIStop G22 PCITRDY G21 [PerAddr03]GPIO14 B04 [PerAddr04]GPIO15 A04 [PerAddr05]GPIO16 A05 PerAddr06 D07 PerAddr07 B06 PerAddr08 A06 ...
Page 21
... PPC405EP – PowerPC 405EP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 9 of 10) Signal Name Ball PerData00 P02 PerData01 N04 PerData02 P01 PerData03 M02 PerData04 M03 PerData05 L02 PerData06 L03 PerData07 K02 PerData08 K03 PerData09 H01 PerData10 J04 PerData11 G02 PerData12 G04 ...
Page 22
... PPC405EP – PowerPC 405EP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 10 of 10) Signal Name Ball SysReset AB20 TCK Y02 TDI AA1 TDO AA2 TestEn V20 TMS AC3 TRST H02 [TS1E]GPIO01 AA23 [TS2E]GPIO02 Y22 [TS1O]GPIO03 Y23 [TS2O]GPIO04 W21 [TS3]GPIO05 U20 [TS4]GPIO06 V23 ...
Page 23
... PPC405EP – PowerPC 405EP Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball A01 GND B01 A02 GND B02 A03 ExtReset B03 A04 GPIO15[PerAddr04] B04 A05 GPIO16[PerAddr05] B05 A06 PerAddr08 B06 A07 GND B07 A08 PerAddr15 B08 A09 GPIO00[PerBLast] ...
Page 24
... PPC405EP – PowerPC 405EP Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball E01 PerWBE1 F01 E02 PHY0Rx1Clk F02 E03 GPIO11[PerCS2] F03 E04 PerCS0 F04 E05 GND F05 OV E06 F06 DD OV E07 F07 DD OV E08 F08 DD E09 GND F09 ...
Page 25
... PPC405EP – PowerPC 405EP Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball J01 GPIO27[UART0_DTR] K01 J02 GPIO28[UART1_Rx] K02 J03 GPIO29[UART1_Tx] K03 J04 PerData10 K04 J05 GND K05 J06 No ball K06 J07 No ball K07 J08 No ball K08 J09 No ball ...
Page 26
... PPC405EP – PowerPC 405EP Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball OV N01 P01 DD N02 UART0_RTS P02 N03 EMC0Tx0D1 P03 N04 PerData01 P04 V N05 P05 DD N06 No ball P06 N07 No ball P07 N08 No ball P08 N09 No ball P09 N10 ...
Page 27
... PPC405EP – PowerPC 405EP Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball U01 GND V01 U02 DQM3 V02 U03 EMC0Tx0D0 V03 U04 MemData25 V04 OV U05 V05 DD U06 No ball V06 U07 No ball V07 U08 No ball V08 U09 No ball V09 ...
Page 28
... PPC405EP – PowerPC 405EP Embedded Processor Table 4. Signals Listed by Ball Assignment Ball Signal Name Ball AA01 TDI AB01 AA02 TDO AB02 AA03 GND AB03 AA04 MemData19 AB04 AA05 EMC0MDIO AB05 AA06 MemData14 AB06 AA07 DQM1 AB07 AA08 MemData10 AB08 AA09 PHY0CrS0 ...
Page 29
... PPC405EP – PowerPC 405EP Embedded Processor Signal List The following table provides a summary of the number of package pins associated with each functional interface group. Table 5. Pin Summary Group Non multiplexed Multiplexed Total Signal Pins Gnd Thermal (and Gnd) Reserved Total Pins In the table “Signal Functional Description” on page 31, each external signal is listed along with a short description of the signal function. Active-low signals (for example, RAS) are marked with an overline. Please see “ ...
Page 30
... As a result, a pull-up resistor should be added to those control signals where an undriven state may affect any devices receiving that particular signal. The following table lists all of the I/O signals provided by the PPC405EP. Please refer to “Signals Listed Alphabetically” on page 13 for the pin number to which each signal is assigned. ...
Page 31
... PPC405EP – PowerPC 405EP Embedded Processor Table 6. Signal Functional Description (Sheet Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. ...
Page 32
... PPC405EP – PowerPC 405EP Embedded Processor Table 6. Signal Functional Description (Sheet Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. ...
Page 33
... PPC405EP – PowerPC 405EP Embedded Processor Table 6. Signal Functional Description (Sheet Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. ...
Page 34
... PPC405EP – PowerPC 405EP Embedded Processor Table 6. Signal Functional Description (Sheet Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. ...
Page 35
... PPC405EP – PowerPC 405EP Embedded Processor Table 6. Signal Functional Description (Sheet Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. ...
Page 36
... PPC405EP – PowerPC 405EP Embedded Processor Table 6. Signal Functional Description (Sheet Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values. ...
Page 37
... PPC405EP – PowerPC 405EP Embedded Processor Table 8. Package Thermal Specifications The PPC405EP is designed to operate within a case temperature range of -40°C to +85°C. Thermal resistance values for the E- PBGA packages in a convection environment are as follows: Package—Thermal Resistance 31mm, 385-balls—Junction-to-Case 1 31mm, 385-balls—Case-to-Ambient Note: 1 ...
Page 38
... PPC405EP – PowerPC 405EP Embedded Processor Table 9. Recommended DC Operating Conditions (Sheet Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Notes: 1. PCI drivers meet PCI specifications. 2. See “5V-Tolerant Input Current” on page 39. ...
Page 39
... PPC405EP – PowerPC 405EP Embedded Processor Figure 3. 5V-Tolerant Input Current 50 0 -50 -100 μ Input Current ( A) -150 -200 -250 -300 -350 0.0 Table 10. Input Capacitance Parameter 3.3V LVTTL I/O 5V tolerant, 3.3V LVTTL I/O PCI I/O Rx only pins IIC pads AMCC 1.0 2.0 3 ...
Page 40
... PPC405EP – PowerPC 405EP Embedded Processor Table 11. DC Electrical Characteristics Parameter Active Operating Current (V )–266MHz DD Active Operating Current (V )–333MHz DD Active Operating Current ( PLL V Input current DD Active Operating Power–266 MHz Active Operating Power–333MHz Note: 1. The maximum current and power values listed above are not guaranteed to be the highest obtainable. These values are dependent on many factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case temperature, and the power supply voltages ...
Page 41
... PPC405EP – PowerPC 405EP Embedded Processor Test Conditions Clock timing and switching characteristics are specified in accordance with operating conditions shown in the table “Recommended DC Operating Conditions.” For all signals other than PCI signals, AC specifications are characterized and the figure at right. For PCI signals there are two different test load circuits, one for the rising edge and one the falling edge as shown in the figures at right ...
Page 42
... PPC405EP – PowerPC 405EP Embedded Processor Table 12. Clocking Specifications Symbol Parameter CPU PF Processor clock frequency C PT Processor clock period C SysClk Input SCF Frequency C SCT Period C SCT Edge stability (phase jitter, cycle to cycle) CS SCT Input high time CH SCT Input low time CL Note: Input slew rate > 2V/ns ...
Page 43
... Ethernet operation is unaffected. 4. IIC operation is unaffected. Caution the system designer to ensure that any SSCG used with the PPC405EP meets the above requirements and does not adversely affect other aspects of the system. AMCC Revision 1.08 – March 24, 2008 ...
Page 44
... PPC405EP – PowerPC 405EP Embedded Processor Table 13. Peripheral Interface Clock Timings Parameter PCIClk input frequency (asynchronous mode) PCIClk period (asynchronous mode) PCIClk input high time PCIClk input low time EMC0MDClk output frequency EMC0MDClk period EMC0MDClk output high time EMC0MDClk output low time ...
Page 45
... PPC405EP – PowerPC 405EP Embedded Processor Figure 5. Input Setup and Hold Timing Waveform System Clock 1.5V Inputs 1.5V Figure 6. Output Delay and Float Timing Waveform System Clock 1. MAX Outputs 1. MIN Outputs 1.5V AMCC MIN MIN Valid Valid MAX Revision 1.08 – March 24, 2008 ...
Page 46
... PPC405EP – PowerPC 405EP Embedded Processor Table 14. I/O Specifications—Group 1 (Sheet Notes: 1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter selected. See the CPC0_EPCTL register PowerPC 405EP Embedded Processor User’ ...
Page 47
... PPC405EP – PowerPC 405EP Embedded Processor Table 14. I/O Specifications—Group 1 (Sheet Notes: 1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Timing shown is with EMAC noise filter selected. See the CPC0_EPCTL register PowerPC 405EP Embedded Processor User’ ...
Page 48
... SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405EP package pin. System designers must use the PPC405EP IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring ...
Page 49
... IIC port. The association of bits in the EEPROM with the configuration values and their default values are covered in detail in the PowerPC 405EP Embedded Processor User’s Manual. Note: If P04 is strapped to 1, and the EEPROM is not connected or is defective, the PPC405EP remains in the reset state and will not boot. ...
Page 50
... PPC405EP – PowerPC 405EP Embedded Processor Document Revision History Revision Date 1.01 07/30/04 Initial Release 1.02 01/10/05 Add lead-free part numbers and clean up AMCC conversion. 1.03 05/01/07 Add information on connection of target device IDSEL to the addess bus. Modify description of TRST signal. Remove note on TrcClk concerning initilization. ...
Page 51
... PPC405EP – PowerPC 405EP Embedded Processor 215 Moffett Park Drive, Sunnyvale, CA 94089 Phone: (408) 542-8600 — (800) 840-6055 — Fax: (408) 542-8601 AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC’ ...