PPC440GP-3FC400C Applied Micro Circuits Corporation, PPC440GP-3FC400C Datasheet
PPC440GP-3FC400C
Specifications of PPC440GP-3FC400C
Related parts for PPC440GP-3FC400C
PPC440GP-3FC400C Summary of contents
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... PCI-X V1.0a interface ( bits 133MHz) with support for conventional PCI V2.2 Description Designed specifically to address high-end embedded applications, the PowerPC 440GP (PPC440GP) provides a high-performance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation. ...
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Power PC 440GP Embedded Processor Contents Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Revision 1.11 – August 27, 2010 Data Sheet Figures PPC440GP Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 25mm, 552-Ball Plastic (FC-PBGA) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 DDR SDRAM MemClkOut0 and Read Clock Delay ...
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... For information on the availability of the following parts, contact your local AppliedMicro sales office. Order Part Numbers Product Order Part Number Name (See Notes and Key drawing) PPC440GP PPC440GP-3FC400C PPC440GP PPC440GP-3FC466C Notes: 1. Package code plastic. 2. Case Temperature Range code -40 °C to +85 °C. 3. All chips are shipped in a tray. ...
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... OPB interfaces up to 66.66MHz, 266MB/s Address Maps The PPC440GP incorporates two address maps. The first is a fixed processor system memory address map. This address map defines the possible contents of various address regions which the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC440GP processor through the use of mtdcr and mfdcr instructions ...
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Power PC 440GP Embedded Processor System Memory Address Map Function DDR SDRAM SRAM 1 Local Memory Reserve EBC Reserved UART0 Reserved UART1 Reserved IIC0 Reserved IIC1 Reserved OPB Arbiter Reserved Internal Peripherals GPIO Controller Ethernet PHY ZMII Ethernet ...
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Revision 1.11 – August 27, 2010 Data Sheet System Memory Address Map Function Reserved PCI-X I/O Reserved PCI-X External Configuration Registers PCI-X Reserved PCI-X Bridge Core Configuration Registers Reserved PCI-X Special Cycle PCI-X Memory Notes: on-chip 1. DDR SDRAM and ...
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Power PC 440GP Embedded Processor DCR Address Map 4KB of Device Configuration Registers Function 1 Total DCR Address Space By function: Reserved Memory Controller External Bus Controller External Bus Master I/F PLB Performance Monitor SRAM Reserved PLB PLB ...
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Revision 1.11 – August 27, 2010 Data Sheet PowerPC 440 Processor Core The PowerPC 440 processor core is designed for high-end applications: RAID controllers, routers, switches, printers, set-top boxes, etc the first processor core to implement the Book ...
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Power PC 440GP Embedded Processor • OPB - Dynamic bus sizing 32-, 16-, and 8-bit data path - Separate and simultaneous read and write data paths - 36-bit address - 66.66MHz, maximum 266MB/s • DCR - 32-bit data ...
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Revision 1.11 – August 27, 2010 Data Sheet • Supports initiation of transfer to the following address spaces: - Single beat I/O reads and writes - Single beat and burst memory reads and writes - Single beat configuration reads and ...
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... Power PC 440GP Embedded Processor Ethernet Controller Interface Ethernet support provided by the PPC440GP interfaces to the physical layer, but the PHY is not included on the chip. Features include: • One or two interfaces running in full- and half-duplex modes at 10Mb/s or 100Mb/s - One full Media Independent Interface (MII) with 4-bit parallel data transfer ...
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Revision 1.11 – August 27, 2010 Data Sheet IIC Bus Interface Features include: • Two IIC interfaces provided • Support for Philips® Semiconductors I • Operation at 100kHz or 400kHz • 8-bit data • 10- or 7-bit address • Slave ...
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Power PC 440GP Embedded Processor JTAG Features include: • IEEE 1149.1 Test Access Port • IBM RISCWatch Debugger support • JTAG Boundary Scan Description Language (BSDL) 14 Revision 1.11 – August 27, 2010 Data Sheet AppliedMicro Proprietary ...
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... Note: All dimensions are in mm. Bottom View 25 0.66 ± 0.1 SOLDERBALL x 552 AppliedMicro Proprietary 440GP – Power PC 440GP Embedded Processor 24 ® PPC440GP Part Number 3xCfffx 25.0 23.0 1.00 TYP 1.214 REF 1 ± 0.3 23.0 7.75 0.5 ± 0.1 0.508 REF 3.191 ± 0.17 15 ...
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Power PC 440GP Embedded Processor Signal Lists The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Multiplexed signals are shown with the default signal (following ...
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Revision 1.11 – August 27, 2010 Data Sheet Signals Listed Alphabetically Signal Name DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 DMAAck0 DMAAck1 DMAAck2 DMAAck3 DMAReq0 DMAReq1 DMAReq2 DMAReq3 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 DrvrInh1 ...
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Power PC 440GP Embedded Processor Signals Listed Alphabetically Signal Name ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMCCD, EMC1RxErr EMCCrS, EMC0CrSDV EMCMDClk EMCMDIO EMCRxClk EMCRxD0, EMC0RxD0 EMCRxD1, EMC0RxD1 EMCRxD2, EMC1RxD0 EMCRxD3, EMC1RxD1 EMCRxDV, EMC1CrSDV EMCRxErr, EMC0RxErr EMCTxClk, ...
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Revision 1.11 – August 27, 2010 Data Sheet Signals Listed Alphabetically Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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Power PC 440GP Embedded Processor Signals Listed Alphabetically Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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Revision 1.11 – August 27, 2010 Data Sheet Signals Listed Alphabetically Signal Name GND GND GND GND GND GND GND GND GND GND GND AppliedMicro Proprietary 440GP – Power PC 440GP Embedded Processor (Sheet 6 of 22) Ball Interface Group ...
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Power PC 440GP Embedded Processor Signals Listed Alphabetically Signal Name [GPIO00]IRQ00 [GPIO01]IRQ01 [GPIO02]IRQ02 [GPIO03]IRQ03 [GPIO04]IRQ04 [GPIO05]IRQ05 [GPIO06]IRQ06 [GPIO07]IRQ07 [GPIO08]IRQ08 [GPIO09]IRQ09 [GPIO10]IRQ10 GPIO11 [GPIO12]UART1_Rx [GPIO13]UART1_Tx [GPIO14]UART1_DSR/CTS [GPIO15]UART1_RTS/DTR [GPIO16]IIC1SClk [GPIO17]IIC1SDA [GPIO18]TrcBS0 [GPIO19]TrcBS1 [GPIO20]TrcBS2 [GPIO21]TrcES0 [GPIO22]TrcES1 [GPIO23]TrcES2 [GPIO24]TrcES3 [GPIO25]TrcES4 [GPIO26]TrcTS0 [GPIO27]TrcTS1 ...
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Revision 1.11 – August 27, 2010 Data Sheet Signals Listed Alphabetically Signal Name HoldReq IIC0SClk IIC0SDA IIC1SClk[GPIO16] IIC1SDA[GPIO17] IRQ00[GPIO00] IRQ01[GPIO01] IRQ02[GPIO02] IRQ03[GPIO03] IRQ04[GPIO04] IRQ05[GPIO05] IRQ06[GPIO06] IRQ07[GPIO07] IRQ08[GPIO08] IRQ09[GPIO09] IRQ10[GPIO10] [IRQ11]PCIReq1 [IRQ12]PCIGnt1 MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 ...
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Power PC 440GP Embedded Processor Signals Listed Alphabetically Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 ...
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Revision 1.11 – August 27, 2010 Data Sheet Signals Listed Alphabetically Signal Name MemData32 MemData33 MemData34 MemData35 MemData36 MemData37 MemData38 MemData39 MemData40 MemData41 MemData42 MemData43 MemData44 MemData45 MemData46 MemData47 MemData48 MemData49 MemData50 MemData51 MemData52 MemData53 MemData54 MemData55 MemData56 MemData57 MemData58 ...
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Power PC 440GP Embedded Processor Signals Listed Alphabetically Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball ...
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Revision 1.11 – August 27, 2010 Data Sheet Signals Listed Alphabetically Signal Name ...
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Power PC 440GP Embedded Processor Signals Listed Alphabetically Signal Name PCIXAD00 PCIXAD01 PCIXAD02 PCIXAD03 PCIXAD04 PCIXAD05 PCIXAD06 PCIXAD07 PCIXAD08 PCIXAD09 PCIXAD10 PCIXAD11 PCIXAD12 PCIXAD13 PCIXAD14 PCIXAD15 PCIXAD16 PCIXAD17 PCIXAD18 PCIXAD19 PCIXAD20 PCIXAD21 PCIXAD22 PCIXAD23 PCIXAD24 PCIXAD25 PCIXAD26 PCIXAD27 ...
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Revision 1.11 – August 27, 2010 Data Sheet Signals Listed Alphabetically Signal Name PCIXAD32 PCIXAD33 PCIXAD34 PCIXAD35 PCIXAD36 PCIXAD37 PCIXAD38 PCIXAD39 PCIXAD40 PCIXAD41 PCIXAD42 PCIXAD43 PCIXAD44 PCIXAD45 PCIXAD46 PCIXAD47 PCIXAD48 PCIXAD49 PCIXAD50 PCIXAD51 PCIXAD52 PCIXAD53 PCIXAD54 PCIXAD55 PCIXAD56 PCIXAD57 PCIXAD58 ...
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Power PC 440GP Embedded Processor Signals Listed Alphabetically Signal Name PCIXC0[BE0] PCIXC1[BE1] PCIXC2[BE2] PCIXC3[BE3] PCIXC4[BE4] PCIXC5[BE5] PCIXC6[BE6] PCIXC7[BE7] PCIXCap PCIXClk PCIXDevSel PCIXFrame PCIXGnt0 PCIXGnt1[IRQ12] PCIXGnt2 PCIXGnt3 PCIXGnt4 PCIXGnt5 PCIXIDSel PCIXINT PCIXIRDY PCIXM66En PCIXParHigh PCIXParLow PCIXPErr PCIXReq0 PCIXReq1[IRQ11] PCIXReq2 ...
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Revision 1.11 – August 27, 2010 Data Sheet Signals Listed Alphabetically Signal Name PCIXStop PCIXTRDY PerAddr00 PerAddr01 PerAddr02 PerAddr03 PerAddr04 PerAddr05 PerAddr06 PerAddr07 PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 ...
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Power PC 440GP Embedded Processor Signals Listed Alphabetically Signal Name PerBLast PerClk PerCS0 PerCS1 PerCS2 PerCS3 PerCS4 PerCS5 PerCS6 PerCS7 32 (Sheet 17 of 22) Ball Interface Group C07 External Slave Peripheral U18 External Master Peripheral E17 L10 ...
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Revision 1.11 – August 27, 2010 Data Sheet Signals Listed Alphabetically Signal Name PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 ...
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Power PC 440GP Embedded Processor Signals Listed Alphabetically Signal Name PerPar0 PerPar1 PerPar2 PerPar3 PerReady[RcvrInh] PerR/W PerWBE0 PerWBE1 PerWBE2 PerWBE3 PerWE RAS [RcvrInh]PerReady RefVEn Reserved Reserved ...
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Revision 1.11 – August 27, 2010 Data Sheet Signals Listed Alphabetically Signal Name TMS TrcBS0[GPIO18] TrcBS1[GPIO19] TrcBS2[GPIO20] TrcClk TrcES0[GPIO21] TrcES1[GPIO22] TrcES2[GPIO23] TrcES3[GPIO24] TrcES4[GPIO25] TrcTS0[GPIO26] TrcTS1[GPIO27] TrcTS2[GPIO28] TrcTS3[GPIO29] TrcTS4[GPIO30] TrcTS5[GPIO31] TrcTS6 TRST UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_DSR/CTS[GPIO14] ...
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Power PC 440GP Embedded Processor Signals Listed Alphabetically Signal Name UARTSerClk ...
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Revision 1.11 – August 27, 2010 Data Sheet Signals Listed Alphabetically Signal Name ...
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Power PC 440GP Embedded Processor In the following table, only the primary (default) signal name is shown for each pin. Multiplexed or multifunction signals are marked with an asterisk (*). To determine what signals or functions are multiplexed ...
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Revision 1.11 – August 27, 2010 Data Sheet Signals Listed by Ball Assignment Ball Signal Name Ball E01 EMCRxD1 * F01 E02 PCIXAD40 F02 E03 PCIXClk F03 E04 PCIXAD49 F04 E05 UART1_RTS/DTR * F05 E06 PCIXAD56 F06 E07 PCIXAD60 F07 ...
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Power PC 440GP Embedded Processor Signals Listed by Ball Assignment Ball Signal Name Ball J01 AGND K01 J02 EMCRxClk K02 J03 EMCTxD3 * K03 J04 EMCTxD2 * K04 J05 PCIXAD37 K05 J06 EMCTxClk * K06 J07 EMCCD * ...
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Revision 1.11 – August 27, 2010 Data Sheet Signals Listed by Ball Assignment Ball Signal Name Ball N01 PerAddr08 P01 N02 GND P02 N03 PerAddr28 P03 V N04 P04 DD N05 DMAAck0 P05 N06 GND P06 N07 PerReady * P07 ...
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Power PC 440GP Embedded Processor Signals Listed by Ball Assignment Ball Signal Name Ball U01 TmrClk V01 U02 GND V02 U03 PerCS7 V03 OV U04 V04 DD U05 MemData63 V05 U06 GND V06 U07 MemData57 V07 V U08 ...
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Revision 1.11 – August 27, 2010 Data Sheet Signals Listed by Ball Assignment Ball Signal Name Ball AA01 MemData48 AB01 AA02 GND AB02 AA03 MemData49 AB03 V AA04 AB04 DD AA05 DQS8 AB05 AA06 GND AB06 AA07 DM5 AB07 SV ...
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... PPC440GP has control of the external bus. When during the course of normal chip operation an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC440GP. In this example, the pins are also bidirectional, serving both as inputs and outputs. ...
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Revision 1.11 – August 27, 2010 Data Sheet Strapping Pins One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation ...
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Power PC 440GP Embedded Processor Signal Functional Description Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V) 3. Must pull down (recommended value is 1kΩ not ...
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Revision 1.11 – August 27, 2010 Data Sheet Signal Functional Description Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V) 3. Must pull down (recommended value is 1kΩ ...
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... PerPar0:3 External peripheral data bus byte parity. PerReady Used by a peripheral slave to indicate it is ready to transfer data. Used by the PPC440GP when not in external master mode, as output by either the peripheral controller or DMA controller depending upon the type of transfer involved. High indicates a PerR/W read from memory, low indicates a write to memory ...
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... Strapping input during reset; pull-up (recommended value is 3kΩ to 3.3V) or pull-down (recommended value is 1kΩ to GND) required Signal Name External Master Peripheral Interface Bus Request. Used when the PPC440GP needs to regain control BusReq of peripheral interface from an external master. External Acknowledgement. Used by the PPC440GP to indicate ExtAck that a data transfer occurred ...
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Power PC 440GP Embedded Processor Signal Functional Description Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V) 3. Must pull down (recommended value is 1kΩ not ...
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Revision 1.11 – August 27, 2010 Data Sheet Signal Functional Description Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V) 3. Must pull down (recommended value is 1kΩ ...
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Power PC 440GP Embedded Processor Signal Functional Description Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V) 3. Must pull down (recommended value is 1kΩ not ...
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... Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case Temperature under bias Notes: 1. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440GP. A separate filter, as shown below, is recommended for each voltage This value is not a specification of the operational temperature range ...
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Power PC 440GP Embedded Processor Recommended DC Operating Conditions Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Parameter Logic Supply Voltage I/O Supply Voltage DDR SDRAM Supply ...
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... REF DD 3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440GP. See “Absolute Maximum Ratings” on page 53. 4. There are power supply power-up sequence requirements. However, external voltage should not be applied ...
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Power PC 440GP Embedded Processor Test Conditions Clock timing and switching characteristics are specified in accordance with operating conditions shown in the table “Recommended DC Operating Conditions.” AC specifications are characterized with V test load as shown in ...
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... Ethernet operation is unaffected. 3. IIC operation is unaffected. Important the system designer to ensure that any SSCG used with the PPC440GP meets the above requirements and does not adversely affect other aspects of the system. AppliedMicro Proprietary 440GP – Power PC 440GP Embedded Processor ...
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Power PC 440GP Embedded Processor Peripheral Interface Clock Timings Parameter PCIXClk input frequency (asynchronous mode) PCIXClk period (asynchronous mode) PCIXClk input high time PCIXClk input low time EMCMDClk output frequency EMCMDClk period EMCMDClk output high time EMCMDClk output ...
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Revision 1.11 – August 27, 2010 Data Sheet Peripheral Interface Clock Timings (Continued) Parameter TmrClk input frequency TmrClk period TmrClk input high time TmrClk input low time Notes the period the OPB clock. The ...
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Power PC 440GP Embedded Processor Input Setup and Hold Waveform Clock Inputs Output Delay and Float Timing Waveform Clock max min Outputs OH High (Drive) Float (High-Z) Low (Drive min T min IS ...
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Revision 1.11 – August 27, 2010 Data Sheet I/O Specifications—All Speeds Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is ...
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Power PC 440GP Embedded Processor I/O Specifications—All Speeds Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns ...
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Revision 1.11 – August 27, 2010 Data Sheet I/O Specifications—All Speeds Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is ...
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Power PC 440GP Embedded Processor I/O Specifications—All Speeds Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns ...
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Revision 1.11 – August 27, 2010 Data Sheet I/O Specifications—400 and 466 MHz Notes: 1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns. Input (ns) Setup Signal Hold Time Time ...
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... The signals are terminated as indicated in the figure below for the DDR timing data in the following sections. DDR SDRAM Simulation Signal Termination Model MemClkOut0 MemClkOut0 PPC440GP Addr/Ctrl/Data/DQS Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data not a recommended physical circuit design for this interface. An actual interface design will depend on many factors, including the type of memory used and the board layout ...
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Revision 1.11 – August 27, 2010 Data Sheet DDR SDRAM Output Driver Specifications Signal Path Write Data MemData00:07 MemData08:15 MemData16:23 MemData24:31 MemData32:39 MemData40:47 MemData48:55 MemData56:63 ECC0:7 DM0:8 MemClkOut0 MemAddr00:12 BA0:1 RAS CAS WE BankSel0:3 ClkEn0:3 DQS0:8 AppliedMicro Proprietary 440GP – ...
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Power PC 440GP Embedded Processor DDR SDRAM Write Operation The following diagram illustrates the relationship among the signals involved with a DDR write operation. DDR SDRAM Write Cycle Timing PLB Clk MemClkOut0 MemClkOut0(90) Addr/Cmd DQS MemData T = ...
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Revision 1.11 – August 27, 2010 Data Sheet I/O Timing—DDR SDRAM T Notes: 1. All of the DQS signals are referenced to MemClkOut0(0). 2. The T values in the table include 3 cycle at the indicated clock speed. ...
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Power PC 440GP Embedded Processor I/O Timing—DDR SDRAM T Notes and T are measured under worst case conditions The time values in the table include 1 cycle at the indicated clock ...
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... In operation, following the receipt of an address and read command from the PPC440GP, the SDRAM generates data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GP using a DQS signal that is delayed 1 cycle. In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency ...
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Power PC 440GP Embedded Processor I/O Timing—DDR SDRAM T Notes Delay from DQS at package pin Stage 1 FF. SIN Delay from data at package pin ...
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... Except for small, low frequency memory systems with the memory located physically close to the PPC440GP unlikely that Stage 1 data can be sampled. When the data comes later necessary to sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing ...
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Power PC 440GP Embedded Processor Example 2: In this example Read Clock is delayed almost 1/2 cycle. Without ECC, Stage 2 data can be sampled at (2). If ECC is enabled, Stage 3 data must be sampled (see ...
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Revision 1.11 – August 27, 2010 Data Sheet Example 3: In this example, ECC is enabled. This requires that Stage 3 data be sampled at (3). If ECC is disabled, the system will still work, but there will be more ...
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... Power PC 440GP Embedded Processor Initialization The PPC440GP provides the option for setting initial parameters based on default values or by reading them from a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered by strapping on external pins (see “Strapping” below). ...
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Revision 1.11 – August 27, 2010 Data Sheet Revision Log Date 08/07/2002 Add revision log. Change EMC0:1TxD0:1 and EMC0:1TxEn T 08/30/2002 09/11/2002 Update for 466 and 500 MHz parts 10/22/2002 Add heat sink mounting information and additional part numbers for ...
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... APPLIEDMICRO SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AppliedMicro and AMCC are Trademarks of Applied Micro Circuits Corporation. Copyright © 2008 Applied Micro Circuits Corporation. All Rights Reserved. 78 Applied Micro Circuits Corporation http://www.appliedmicro.com Revision 1.11 – ...