PPC405GP-3KE200C Applied Micro Circuits Corporation, PPC405GP-3KE200C Datasheet
PPC405GP-3KE200C
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PPC405GP-3KE200C Summary of contents
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... UART and memory - Scatter-gather chaining supported - Four channels Description Designed specifically to address embedded applications, the PowerPC 405GP (PPC405GP) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-performance RISC ...
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... Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 I/O Specifications—All speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 I/O Specifications—133 and 200MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I/O Specifications—266MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 PPC405GP Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2 Revision 2.05 – August 19, 2008 Data Sheet AMCC ...
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... Revision 2.05 – August 19, 2008 Data Sheet Figures PPC405GP Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 27mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 35mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5V-Tolerant Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 AMCC 405GP – Power PC 405GP Embedded Processor ...
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... PPC405GP-3KE133C PPC405GP PPC405GP-3KE133CZ PPC405GP PPC405GP-3BE200C PPC405GP PPC405GP-3BE200CZ PPC405GP PPC405GP-3DE200C PPC405GP PPC405GP-3DE200CZ PPC405GP PPC405GP-3FE200C PPC405GP PPC405GP-3FE200CZ PPC405GP PPC405GP-3KE200C PPC405GP PPC405GP-3KE200CZ PPC405GP PPC405GP-3BE266C PPC405GP PPC405GP-3BE266CZ PPC405GP PPC405GP-3DE266C PPC405GP PPC405GP-3DE266CZ PPC405GP PPC405GP-3FE266C PPC405GP PPC405GP-3FE266CZ PPC405GP PPC405GP-3KE266C PPC405GP PPC405GP-3KE266CZ Notes the end of the Order Part Number indicates a tape-and-reel shipping package. Otherwise, the chips are shipped in a tray. ...
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... Grade 3 Reliability Package B: 35mm, 456 E-PBGA D: 27mm, 456 E-PBGA F: 35mm, 456 E-PBGA lead-free K: 27mm, 456 E-PBGA lead-free AMCC 405GP – Power PC 405GP Embedded Processor PPC405GP-3BE266Cx Shipping Package Blank = Tray Z = Tape and reel Operational Case Temperature Range (-40°C to +85°C) Processor Speed ...
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... Arb Code Decompression (CodePack™) SDRAM Controller 13-bit addr 32-bit data The PPC405GP is designed using the IBM blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnect 6 OCM Power SRAM Mgmt DCRs ...
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... The PPC405GP incorporates two simple and separate address maps. The first address map defines the possible use of address regions that the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC405GP processor through the use of mtdcr and mfdcr instructions. ...
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Power PC 405GP Embedded Processor DCR Address Map 4KB Device Configuration Registers Function 1 Total DCR Address Space By function: Reserved Memory Controller Registers External Bus Controller Registers Decompression Controller Registers Reserved On-Chip Memory Controller Registers Reserved PLB ...
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Revision 2.05 – August 19, 2008 Data Sheet On-Chip Memory (OCM) The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the processor core. Features include: • Low-latency access to critical instructions and data ...
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... Supports PowerPC processor boot from PCI memory SDRAM Memory Controller The PPC405GP Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to four physical banks 256MB per bank are supported maximum of 1GB. Memory timings, address and bank sizes, and memory addressing modes are programmable ...
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Revision 2.05 – August 19, 2008 Data Sheet • Peripheral Device pacing with external “Ready” • External master interface - Write posting from external master - Read prefetching on PLB for external master reads - Bursting capable from external master ...
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Power PC 405GP Embedded Processor IIC Bus Interface • Compliant with Philips® Semiconductors I • Operation at 100kHz or 400kHz • 8-bit data • 10- or 7-bit address • Slave transmitter and receiver • Master transmitter and receiver ...
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Revision 2.05 – August 19, 2008 Data Sheet Universal Interrupt Controller (UIC) The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the local PowerPC processor. Features include: • Supports seven ...
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... SOLDERBALL x 456 14 Part Number 24 TYP A 27.0 25.0 1.0 TYP Thermal Balls PCB Substrate ∅ 0. ∅ 0. Revision 2.05 – August 19, 2008 Data Sheet Logo View ® PPC405GP 1YWWBZZZZZ CCCCCCC Lot Number C 0. 0.25 0.35 C Mold Compound ± 0.5 0.1 2.65 max AMCC ...
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... SOLDERBALL x 456 AMCC 405GP – Power PC 405GP Embedded Processor Part Number 30.0 Typ A 35.0 31.75 1.27 PCB Substrate 2.65 max ∅ 0. ∅ 0. Logo View ® PPC405GP 1YWWBZZZZZ CCCCCCC Lot Number C 0. 0.25 0.35 C Mold Compound ± 0.6 0.1 15 ...
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... Power PC 405GP Embedded Processor Pin Lists The PPC405GP embedded controller is available as a 456-ball E-PBGA. The 456-ball package is available in two sizes—35 millimeters and 27 millimeters. In this section there are two tables that correlate the external signals to the physical package pin (ball) on which they appear. ...
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Revision 2.05 – August 19, 2008 Data Sheet Signals Listed Alphabetically Signal Name Ball EMCTxEn K23 EMCTxErr K25 EOT0/TC0 F3 EOT1/TC1 G2 EOT2/TC2 V2 EOT3/TC3 Y1 ExtAck Y3 ExtReq Y4 ExtReset A11 A16 A19 A21 A26 ...
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Power PC 405GP Embedded Processor Signals Listed Alphabetically Signal Name Ball AB9 AB13 AB14 AB18 AB22 AC4 AC23 AD3 AD24 AE1 GND AE2 AE25 AF1 AF6 AF8 AF11 AF16 AF21 AF25 AF26 Gnt[PCIReq0] C19 GPIO1[TS1E] D18 GPIO2[TS2E] C20 ...
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Revision 2.05 – August 19, 2008 Data Sheet Signals Listed Alphabetically Signal Name Ball MemAddr0 AE22 MemAddr1 AC21 MemAddr2 AE21 MemAddr3 AD21 MemAddr4 AF22 MemAddr5 AE20 MemAddr6 AC19 MemAddr7 AE19 MemAddr8 AD19 MemAddr9 AC18 MemAddr10 AF19 MemAddr11 AD18 MemAddr12 AC17 ...
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Power PC 405GP Embedded Processor Signals Listed Alphabetically Signal Name Ball B17 C13 E19 E20 E21 F5 F22 G5 G22 H5 H22 K2 N24 U25 W5 W22 Y5 Y22 AA5 AA22 AB6 ...
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Revision 2.05 – August 19, 2008 Data Sheet Signals Listed Alphabetically Signal Name Ball PCIClk B20 PCIDevSel H25 PCIFrame J24 PCIGnt0[Req] U23 PCIGnt1 T23 PCIGnt2 F23 PCIGnt3 H26 PCIGnt4 N23 PCIGnt5 M24 PCIIDSel P26 PCIINT[PerWE] C23 PCIIRDY J23 PCIParity E26 ...
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Power PC 405GP Embedded Processor Signals Listed Alphabetically Signal Name Ball PerCS0 B3 PerCS1[GPIO10] C4 PerCS2[GPIO11] C5 PerCS3[GPIO12] A4 PerCS4[GPIO13] B9 PerCS5[GPIO14] B10 PerCS6[GPIO15] A9 PerCS7[GPIO16] B11 PerData0 U4 PerData1 U3 PerData2 U1 PerData3 T4 PerData4 R2 PerData5 ...
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Revision 2.05 – August 19, 2008 Data Sheet Signals Listed Alphabetically Signal Name Ball PHYRxErr U24 PHYTxClk E25 RAS AF24 RcvrInh C25 Y23 Y26 Reserved 1 AF4 Req[PCIGnt0] U23 SysClk A25 SysErr AD25 SysReset D22 TCK AD22 TDI AE24 TDO ...
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Power PC 405GP Embedded Processor Signals Listed Alphabetically Signal Name Ball E10 E11 E12 E15 E16 E17 K5 K22 L5 L22 M5 M22 R22 T5 T22 U5 U22 AB10 AB11 AB12 AB15 AB16 AB17 WE ...
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Revision 2.05 – August 19, 2008 Data Sheet Signals Listed by Ball Assignment—456-Ball Package Ball Signal Name Ball A1 GND B14 A2 GND B15 A3 PerAddr1 B16 A4 PerCS3[GPIO12] B17 A5 PerAddr8 B18 A6 GND B19 A7 DMAReq3 B20 A8 ...
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Power PC 405GP Embedded Processor Signals Listed by Ball Assignment—456-Ball Package Ball Signal Name Ball J1 PerData23 M5 J2 PerData26 M11 J3 PerData25 M12 J4 PerData27 M13 J5 GND M14 J22 GND M15 J23 PCIIRDY M16 J24 PCIFrame ...
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Revision 2.05 – August 19, 2008 Data Sheet Signals Listed by Ball Assignment—456-Ball Package Ball Signal Name Ball AA25 PHYCol AC8 AA26 GND AC9 AB1 MemData24 AC10 AB2 MemData21 AC11 AB3 GPIO9[TrcClk] AC12 AB4 UART0_CTS AC13 AB5 GND AC14 OV ...
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... PPC405GP has control of the external bus. When, during the course of normal chip operation, an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC405GP. In this example, the pins are also bidirectional, serving as both inputs and outputs. ...
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... When the PCI bridge is unused, configure the PCI controller to park on the bus and actively drive PCIAD31:0, PCIC3:0[BE3:0], and the remaining PCI control signals by doing the following: - Strap the PPC405GP to disable the internal PCI arbiter and to operate the PCI interface in synchronous mode. ...
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Power PC 405GP Embedded Processor Signal Functional Description Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down ...
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Revision 2.05 – August 19, 2008 Data Sheet Signal Functional Description Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and ...
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... MemClkOut0:1 SDRAM attach without requiring this signal to be repowered by a PLL or zero-delay buffer. External Slave Peripheral Interface Peripheral data bus used by PPC405GP when not in external master mode, otherwise used by external master. PerData0:31 Note: PerData0 is the most significant bit (msb) on this bus. ...
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... When the PPC405GP is the bus master, it enables the selected device to drive the bus. Used by the PPC405GP when not in external master mode, as output by either the peripheral controller or DMA controller depending upon the type of transfer involved. High indicates a read from memory, low PerR/W indicates a write to memory ...
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... HoldPri master tenure. Used when the PPC405GP needs to regain control of peripheral BusReq interface from an external master. An input used to indicate to the PPC405GP that an external slave PerErr peripheral error occurred. Internal Peripheral Interface Serial Clock used to provide an alternate clock to the internally generated serial clock. Used in cases where the allowable internally UARTSerClk generated baud rates are not satisfactory ...
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... JTAG test clock. The frequency of this input can range from DC to TCK 25MHz. JTAG reset. TRST must be low at power-on to initialize the JTAG TRST controller and for normal operation of the PPC405GP. System Interface SysClk Main system clock input. Main system reset. External logic can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset ...
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Power PC 405GP Embedded Processor Signal Functional Description Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down ...
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Revision 2.05 – August 19, 2008 Data Sheet Signal Functional Description Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and ...
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... Notes: 2. All specified voltages are with respect to GND. Package Thermal Specifications The PPC405GP is designed to operate within a case temperature range of -40°C to +85°C. Thermal resistance values for the E-PBGA packages (leaded and lead-free convection environment are as follows: Package—Thermal Resistance 35mm, 456-balls—Junction-to-Case 35mm, 456-balls— ...
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Revision 2.05 – August 19, 2008 Data Sheet Recommended DC Operating Conditions Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Notes: 1. PCI drivers meet PCI specifications. 2. See ...
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Power PC 405GP Embedded Processor 5V-Tolerant Input Current 100 0 -100 -200 -300 -400 -500 -600 -700 0.0 1.0 Input Capacitance Parameter 3.3V LVTTL I/O 5V tolerant LVTTL I/O PCI I/O Rx only pins 40 2.0 3.0 4.0 ...
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Revision 2.05 – August 19, 2008 Data Sheet DC Electrical Characteristics Parameter Active Operating Current (V )–133MHz DD Active Operating Current (V )–200MHz DD Active Operating Current (V )–266 MHz DD Active Operating Current (OV )–133MHz DD Active Operating Current ...
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Power PC 405GP Embedded Processor Clocking Specifications Symbol Parameter CPU PF Processor clock frequency C PT Processor clock period C SysClk Input SCF Clock input frequency C SCT Clock period C SCT Clock edge stability (phase jitter, cycle ...
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... Ethernet operation is unaffected. 4. IIC operation is unaffected. Caution the system designer to ensure that any SSCG used with the PPC405GP meets the above requirements and does not adversely affect other aspects of the system. AMCC 405GP – Power PC 405GP Embedded Processor ...
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Power PC 405GP Embedded Processor Peripheral Interface Clock Timings Parameter PCIClk input frequency (asynchronous mode) PCIClk period (asynchronous mode) PCI Clock frequency (synchronous mode) PCI Clock period (synchronous mode - Note 2) PCIClk input high time PCIClk input ...
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Revision 2.05 – August 19, 2008 Data Sheet Input Setup and Hold Waveform Clock Inputs Output Delay and Float Timing Waveform Clock T max OV T min Outputs OH High (Drive) Float (High-Z) Low (Drive) AMCC 405GP – Power PC ...
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Power PC 405GP Embedded Processor Notes all of the following I/O Specifications tables a timing values of “na” means “not applicable” and “dc” means “don’t care.” 2. See “Test Conditions” on page 41 for output capacitive ...
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Revision 2.05 – August 19, 2008 Data Sheet I/O Specifications—All speeds Notes: 1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. In synchronous mode, timing is relative ...
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... SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405GP package pin. System designers must use the PPC405GP IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring ...
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... SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405GP package pin. System designers must use the PPC405GP IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring ...
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... When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is read to enable default initial conditions prior to PPC405GP start-up. The actual capture instant is the nearest SysClk edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3kΩ ...
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... The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the PPC405GP. These bits are shown for information only; and do not require modification except in special clocking circumstances such as spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GP, visit the technical documents area of the AMCC PowerPC web site. 2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “ ...
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Power PC 405GP Embedded Processor Revision Log Date 02/12/2003 Timing diagram update 04/14/2003 Update legal statements regarding document status. 06/19/2003 Add 133 MHz part numbers. 12/02/2004 Update to AMCC format. Add lead-free PNs. 01/06/2005 Correct typographical error in ...
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Revision 2.05 – August 19, 2008 Data Sheet Printed in the United States of America, August 2008 The following are trademarks of AMCC in the United States, or other countries, or both: AMCC Other company, product, and service names may ...
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... AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2008 Applied Micro Circuits Corporation. 54 Applied Micro Circuits Corporation http://www.amcc.com Revision 2.05 – ...