PPC440EP-3JC533C Applied Micro Circuits Corporation, PPC440EP-3JC533C Datasheet
PPC440EP-3JC533C
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PPC440EP-3JC533C Summary of contents
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... Programmable General Purpose Timers (GPT). Description Designed specifically to address high-end embedded applications, the PowerPC 440EP (PPC440EP) provides a high-performance, low- power solution that interfaces to a wide range of peripherals and incorporates on-chip power management features. This chip contains a high-performance RISC ...
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... General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Universal Interrupt Controller (UIC JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 DDR1 SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 2 440EP – PPC440EP Embedded Processor AMCC Proprietary ...
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... PPC440EP Embedded Processor Figures Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. PPC440EP Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. 35mm, 456-Ball E-PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 4. Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 5. Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 6. Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 7. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 8. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 9 ...
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... Revision 1.29 – May 07, 2008 Data Sheet Table 25. I/O Timing—DDR SDRAM T Table 26. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4 440EP – PPC440EP Embedded Processor and SIN DIN AMCC Proprietary ...
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... The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. Refer to the PPC440EP User’s Manual for details on accessing these registers. Figure 1. Order Part Number Key ...
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... Controller USB 2.0 266MHz data rate Device - 13-bit addr UTMI 1.1PHY - 32-bit data D+/D− The PPC440EP is a system on a chip (SOC) using IBM CoreConnect Bus 6 440EP – PPC440EP Embedded Processor Power Mgmt 66MHz max DCRs - 30-bit addr - 16-bit data DCR Bus ...
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... PPC440EP Embedded Processor Address Maps The PPC440EP incorporates two address maps. The first is a fixed processor System Memory Address Map. This address map defines the possible contents of various address regions which the processor can access. The second is the DCR Address Map for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC440EP processor through the use of mtdcr and mfdcr instructions ...
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... Boot space (EBC Bank 0 and PCI) Notes: 1. DDR SDRAM can be located anywhere in the Local Memory area of the memory map. 2. EBC and PCI are relocatable, but this map reflects the suggested configuration. 8 440EP – PPC440EP Embedded Processor Sub Function Start Address 0 EF50 0000 0 EF60 0000 ...
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... PPC440EP Embedded Processor Table 2. DCR Address Map (4KB of Device Configuration Registers) Function 1 Total DCR Address Space By function: Reserved Clocking Power On Reset (CPR) System DCRs (SDR) Memory Controller (SDRAM) External Bus Controller (EBC) Reserved PLB 128 Performance Monitor (PPM) Reserved ...
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... MAC Floating Point Unit (FPU) Features include: • Five stages with 2 MFlops/MHz • Hardware support for IEEE 754 • Single- and double-precision • Single-cycle throughput on most instructions • Thirty-two 64-bit floating point registers 10 440EP – PPC440EP Embedded Processor AMCC Proprietary ...
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... PPC440EP Embedded Processor Internal Buses The PowerPC 440EP features five standard on-chip buses: two Processor Local Buses (PLBs), two On-Chip Peripheral Buses (OPBs), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the PCI bridge connect to the PLBs ...
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... CAS latencies of 2, 2.5 and 3 supported • DDR200/266 support • Page mode accesses (up to eight open pages) with configurable paging policy • Programmable address mapping and timing • Hardware and software initiated self-refresh • Power management (self-refresh, suspend, sleep) 12 440EP – PPC440EP Embedded Processor AMCC Proprietary ...
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... External master can control EBC slaves for own access and control Ethernet Controller Interface Ethernet support provided by the PPC440EP interfaces to the physical layer but the PHY is not included on the chip: • One to two 10/100 interfaces running in full- and half-duplex modes – ...
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... One programmable interrupt request signal • Provides full management of all IIC bus protocols • Programmable error recovery • Includes an integrated boot-strap controller (BSC) that is multiplexed with the IIC0 interface 14 440EP – PPC440EP Embedded Processor 2 C Specification, dated 1995 AMCC Proprietary ...
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... PPC440EP Embedded Processor Serial Peripheral Interface (SPI/SCP) The Serial Peripheral Interface (also known as the Serial Communications Port full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is a master on the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB. ...
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... Programmable interrupt priority ordering • Programmable critical interrupt vector for faster vector processing JTAG Features include: • IEEE 1149.1 Test Access Port • IBM RISCWatch Debugger support • JTAG Boundary Scan Description Language (BSDL) 16 440EP – PPC440EP Embedded Processor AMCC Proprietary ...
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... PPC440EP Embedded Processor Package Diagram Figure 3. 35mm, 456-Ball E-PBGA Top View PPC440EP Part Number 1YWWBZZZZZ Lot Number Gold Gate Release Corresponds to A1 Ball Location Notes: 1. All dimensions are in mm. 2. Package is available in both lead-free and leaded versions. 0.20 Bottom View ...
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... Time within 5°C of Actual Peak Temperature Ramp-down Rate Time 25°C to Peak Temperature Table 4. JEDEC Moisture Sensitivity Level and Ball Composition MSL Level Solder Ball Metallurgy 18 440EP – PPC440EP Embedded Processor Sn-Pb Eutectic Assembly 3°C/second max 100°C 150°C 60-120 Seconds 183°C 60-150 Seconds 225 +0/-5° ...
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... PPC440EP Embedded Processor Signal Lists The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and alternate signals in brackets. Multiplexed signals appear alphabetically multiple times in the list— ...
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... EMC1TxD0]GPIO18[NFCLE] [EMCTxD3, EMC1TxD1]GPIO19[NFALE] [EMCTxEn, EMC0TxEn, EMCSync]GPIO24 [EMCTxErr, EMC1TxEn]GPIO23[NFWEn] [EOT0/TC0][IRQ9]GPIO48 [EOT1/TC1][IRQ6]GPIO45 [EOT2/TC2][PerAddr05]GPIO02 [EOT3/TC3][PerAddr02]GPIO05 [ExtAck][USB2XcvrSel]GPIO30 [ExtReq][USB2RxErr]GPIO27 ExtReset 20 440EP – PPC440EP Embedded Processor Ball Interface Group P02 N02 M01 M02 DDR SDRAM N03 N04 L02 M03 AC16 ...
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... PPC440EP Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 3 of 24) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 22 440EP – PPC440EP Embedded Processor Ball Interface Group M15 M25 N05 N11 N13 N14 N15 N16 P11 P12 P13 P14 P16 P22 R12 R14 ...
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... PPC440EP Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 5 of 24) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND AMCC Proprietary Revision 1.29 – May 07, 2008 Data Sheet Ball Interface Group AD03 AD24 AE01 AE02 ...
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... GPIO21[EMCDV, EMC1CrsDV][NFREn] GPIO22[EMCCrS, EMC0CrsDV] GPIO23[EMCTxErr, EMC1TxEn][NFWEn] GPIO24[EMCTxEn, EMC0TxEn, EMCSync] GPIO25[EMCCD, EMC1RxErr][NFRdyBusy] GPIO26[USB2RxDV] GPIO27[USB2RxErr][ExtReq] GPIO28[USB2TxVal] GPIO29[USB2Susp][HoldAck] GPIO30[USB2XcvrSel][ExtAck] GPIO31[USB2TermSel][BusReq] 24 440EP – PPC440EP Embedded Processor Ball Interface Group C08 B06 A05 D08 C07 B04 C06 A04 B07 ...
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... PPC440EP Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 7 of 24) Signal Name GPIO32[USB2OM0] GPIO33[USB2OM1] GPIO34[UART0_DCD/UART1_CTS/UART2_Tx] GPIO35[UART0_DSR/UART1_RTS/UART2_Rx] GPIO36[UART0_CTS/UART3_Rx] GPIO37[UART0_RTS/UART3_Tx] GPIO38[UART0_DTR/UART1_Tx] GPIO39[UART0_RI/UART1_Rx] GPIO40[IRQ0] GPIO41[IRQ1] GPIO42[IRQ2] GPIO43[IRQ3] GPIO44[IRQ4][DMAAck1] GPIO45[IRQ6][EOT1/TC1] GPIO46[IRQ7][DMAReq0] GPIO47[IRQ8][DMAAck0] GPIO48[IRQ9][EOT0/TC0] GPIO49[TrcBS0] GPIO50[TrcBS1] GPIO51[TrcBS2] GPIO52[TrcES0] GPIO53[TrcES1] GPIO54[TrcES2] ...
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... MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut0 26 440EP – PPC440EP Embedded Processor Ball Interface Group U24 IIC1 Peripheral V25 D03 G04 F02 G02 G25 Interrupts AC12 H23 B24 D18 A19 V24 ...
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... PPC440EP Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 9 of 24) Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 ...
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... No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball 28 440EP – PPC440EP Embedded Processor Ball Interface Group AC14 D06 C06 A04 B07 NAND Flash AF14 AC16 AF17 AF18 F06 F07 F08 F09 F10 ...
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... PPC440EP Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 11 of 24) Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball ...
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... No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball 30 440EP – PPC440EP Embedded Processor Ball Interface Group J20 J21 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 ...
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... PPC440EP Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 13 of 24) Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball ...
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... No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball 32 440EP – PPC440EP Embedded Processor Ball Interface Group T09 T10 T17 T18 T19 T20 T21 U06 U07 U08 U09 U10 U11 U12 U13 U14 ...
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... PPC440EP Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 15 of 24) Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball ...
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... 440EP – PPC440EP Embedded Processor Ball Interface Group AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 A physical ball does not exist at these ball coordinates. AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 E06 E07 E08 E13 E19 E20 E21 F05 F22 ...
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... PPC440EP Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 17 of 24) Signal Name PCIAD00 PCIAD01 PCIAD02 PCIAD03 PCIAD04 PCIAD05 PCIAD06 PCIAD07 PCIAD08 PCIAD09 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 ...
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... PCIGnt4 PCIGnt5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr PCIReq0/Gnt PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr PCIStop PCITRDY 36 440EP – PPC440EP Embedded Processor Ball Interface Group D17 L24 A25 PCI D25 H25 E24 G26 PCI D20 PCI E25 PCI C23 PCI D24 ...
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... PPC440EP Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 19 of 24) Signal Name [PerAddr02]GPIO05[EOT3/TC3] [PerAddr03]GPIO04[DMAAck3] [PerAddr04]GPIO03[DMAReq3] [PerAddr05]GPIO02[EOT2/TC2] [PerAddr06]GPIO01[DMAAck2] [PerAddr07]GPIO00[DMAReq2] PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 ...
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... PerOE PerReady PerR/W PerWBE0 PerWBE1 PSROOut RAS [RcvrInh]USB2RxAct[HoldReq] [RefEn]USB2TxRdy [RejectPkt]USB2LS0[DrvrInh1] SAGND SAV DD SCPClkOut[IIC1SClk] SCPDI[IIC1SData] SCPDO 38 440EP – PPC440EP Embedded Processor Ball Interface Group H01 K04 G01 J03 J04 H03 E01 G03 External Slave Peripheral H04 E02 D01 F03 C01 F04 ...
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... PPC440EP Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 21 of 24) Signal Name REF1 SV REF2A SV REF2B SysClk SysErr SysReset TCK TDI TDO TestEn TmrClk TMS [TrcBS0]GPIO49 [TrcBS1]GPIO50 [TrcBS2]GPIO51 TrcClk AMCC Proprietary Revision 1.29 – May 07, 2008 Data Sheet Ball Interface Group ...
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... TRST [UART0_CTS/UART3_Rx]GPIO36 [UART0_RTS/UART3_Tx]GPIO37 UART0_Rx UART0_Tx [UART0_DCD/UART1_CTS/UART2_Tx]GPIO34 [UART0_DSR/UART1_RTS/UART2_Rx]GPIO35 [UART0_DTR/UART1_Tx]GPIO38 [UART0_RI/UART1_Rx]GPIO39 UARTSerClk 40 440EP – PPC440EP Embedded Processor Ball Interface Group Y03 AA04 AB03 Trace AB04 AF22 AC22 AE24 AD04 AD06 Trace AC09 AD12 AE15 D07 JTAG ...
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... PPC440EP Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 23 of 24) Signal Name USB1Clk USB1DevXcvr USB1DevXcvr USB1HostXcvr USB1HostXcvr USB2Clk USB2DI0 USB2DI1 USB2DI2 USB2DI3 USB2DI4 USB2DI5 USB2DI6 USB2DI7 USB2DO0 USB2DO1 USB2DO2 USB2DO3 USB2DO4 USB2DO5 USB2DO6 USB2DO7 USB2LS0[DrvrInh1][RejectPkt] USB2LS1[LeakTest][HoldPri] [USB2OM0]GPIO32 [USB2OM1]GPIO33 ...
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... 440EP – PPC440EP Embedded Processor Ball Interface Group E05 E10 E11 E12 E15 E16 E17 E22 K05 K22 L05 L22 M05 M22 M14 N12 Power P15 R05 R13 R22 T05 T22 U05 U22 AB05 AB10 AB11 AB12 AB15 AB16 AB17 AB22 ...
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... PPC440EP Embedded Processor In the following table, only the primary (default) signal name is shown for each pin. Multiplexed or multifunction signals are marked with an asterisk (*). To determine what signals or functions are multiplexed on those pins, look up the primary signal name in Table 5, Signals Listed Alphabetically. ...
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... E21 F21 DD V E22 F22 DD E23 PCIStop F23 E24 PCIGnt5 F24 E25 PCIIRDY F25 E26 PCIC3/BE3 F26 44 440EP – PPC440EP Embedded Processor Signal Name Ball Signal Name GND G01 PerData02 GPIO42* G02 GPIO43* PerData11 G03 PerData07 PerData13 G04 GPIO41 G05 DD DD ...
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... PPC440EP Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball J01 DM2 K01 J02 CAS K02 J03 PerData03 K03 J04 PerData04 K04 J05 GND K05 J06 No ball K06 J07 No ball K07 J08 No ball K08 J09 No ball ...
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... N21 No ball P21 OV N22 P22 DD N23 PCIAD28 P23 N24 GPIO38* P24 N25 PCIReq0/Gnt P25 N26 PCIAD29 P26 46 440EP – PPC440EP Embedded Processor Signal Name Ball Signal Name MemAddr00 R01 BankSel2 ECC0 R02 BankSel1 SV R03 MemAddr10 REF2A MemAddr01 R04 BankSel0 SV V R05 ...
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... PPC440EP Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball U01 MemAddr04 V01 U02 MemData31 V02 U03 MemData29 V03 U04 MemAddr06 V04 V U05 V05 DD U06 No ball V06 U07 No ball V07 U08 No ball V08 U09 No ball V09 ...
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... AA21 No ball AB21 SV AA22 AB22 DD AA23 GPIO31* AB23 AA24 GPIO51* AB24 AA25 GPIO30* AB25 AA26 GND AB26 48 440EP – PPC440EP Embedded Processor Signal Name Ball Signal Name SysErr AC01 GND MemAddr09 AC02 MemData20 GPIO54* AC03 MemData19 GPIO55* AC04 GND V AC05 MemData17 DD ...
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... PPC440EP Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball AE01 GND AF01 AE02 GND AF02 AE03 MemData16 AF03 AE04 MemSelfRef AF04 AE05 DM0 AF05 SV AE06 AF06 REF2B AE07 MemData13 AF07 AE08 MemData11 AF08 AE09 MemData08 ...
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... PPC440EP has control of the external bus. When during the course of normal chip operation an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC440EP. In this example, the pins are also bidirectional, serving both as inputs and outputs. ...
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... PPC440EP Embedded Processor Multimode Signals In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin has multiple signal names assigned to distinguish different modes of operation, all of the names are shown. Strapping Pins One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see “ ...
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... T arget agent’s ability to complete the current data phase of the transaction. PCITRDY (PCI 2.2 specification requires 8.2kΩ pull up on host system) 52 440EP – PPC440EP Embedded Processor Description . I/O Type Notes I/O 3 ...
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... PPC440EP Embedded Processor Table 8. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ to 3.3V not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
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... SMII: Sync signal. (Note: Redrive EMCSync when driving more EMCSync than one load. EMCSync is a weak driver). EMCTxErr, MII: Transmit error. EMC1TxEn RMII1: Transmit data enabled. RejectPkt External request to reject a packet. 54 440EP – PPC440EP Embedded Processor Description I/O Type Notes 3.3V tolerant I/O 2.5V CMOS 3.3V tolerant I/O 2 ...
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... Note: PerData00 is the most significant bit (msb) on this bus. Used by either peripheral controller or DMA controller depending PerOE upon the type of transfer involved. When the PPC440EP is the bus master, it enables the selected device to drive the bus. PerReady Used by a peripheral slave to indicate it is ready to transfer data. ...
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... If not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset; pull-up or pull-down required Signal Name External Master Peripheral Interface Bus Request. Used when the PPC440EP needs to regain control BusReq of peripheral interface from an external master. External Acknowledgement. Used by the PPC440EP to indicate ExtAck that a data transfer occurred ...
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... PPC440EP Embedded Processor Table 8. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ to 3.3V not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
Page 58
... TMS Test Mode Select. Test Reset. Note: Must be asserted low during a power-on system reset in TRST order to reset the JTAG interface. If the JTAG interface is not reset, the processor may not boot. 58 440EP – PPC440EP Embedded Processor Description I/O Type Notes O Multiplex O Multiplex ...
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... PPC440EP Embedded Processor Table 8. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ to 3.3V not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
Page 60
... PLLs (analog). DD AGND PLL (analog) voltage ground. SAV 1.5V—Filtered voltage for memory PLL (analog). DD SAGND PLL (analog) memory voltage ground. 60 440EP – PPC440EP Embedded Processor Description I/O Type Notes 3.3V tolerant I/O 2.5V CMOS 3.3V tolerant O 2 ...
Page 61
... PPC440EP Embedded Processor Device Characteristics Table 9. Absolute Maximum Ratings The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device. None of the performance specification contained in this document are guaranteed when operating at these maximum ratings ...
Page 62
... DD 3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440EP. See “Absolute Maximum Ratings” on page 61. 4. Overshoot and undershoot voltages are for 10% duty cycle. 5. The time for overshoot or undershoot is time above OV 62 440EP – ...
Page 63
... DD DD Analog Voltage Filter The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440EP. A Separate filter, as shown below, is recommended for each voltage. • The filter should keep the AV DD mV. ...
Page 64
... Notes: 1. Typical Power is based on nominal voltage of V test application that exercises each core with representative traffic. 64 440EP – PPC440EP Embedded Processor DD AV SAV DD – SMT ferrite bead chip, Murata BLM21PG600SN1 μ C – 0.1 F ceramic AGND, SAGND ...
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... PPC440EP Embedded Processor Table 14. V Supply Power Dissipation DD Frequency (MHz) 333 400 533 667 Notes: 1. Power is based on V specified in the table and T DD that exercises each core with representative traffic. Table 15. DC Power Supply Current Loads Parameter V (1.5V) active operating current ...
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... Phone: 408-567-8082 Test Conditions Clock timing and switching characteristics are specified in accordance with operating conditions shown in the table “Recommended DC Operating Conditions.” AC specifications are characterized with V shown in the figure to the right. 66 440EP – PPC440EP Embedded Processor Symbol Package 0 (0) θ E-PBGA 20.0 JA θ ...
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... PPC440EP Embedded Processor Table 17. Clocking Specifications Symbol Parameter SysClk Input F Frequency C T Period C T Edge stability (cycle-to-cycle jitter High time CH T Low time CL ≥ Note: Input slew rate 1V/ns CPU Clock F Frequency C MemClkOut and PLB Clock F Frequency C T Period ...
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... Ethernet operation is unaffected. 3. IIC operation is unaffected. Important the system designer to ensure that any SSCG used with the PPC440EP meets the above requirements and does not adversely affect other aspects of the system. 68 440EP – PPC440EP Embedded Processor ...
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... PPC440EP Embedded Processor I/O Specifications Table 18. Peripheral Interface Clock Timings Parameter PCIClk input frequency (asynchronous mode) PCIClk period (asynchronous mode) PCIClk input high time PCIClk input low time EMCMDClk output frequency EMCMDClk period EMCMDClk output high time EMCMDClk output low time ...
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... Figure 7. Output Delay and Float Timing Waveform Clock 1.25V T max OV T min Outputs OH High (Drive) Float (High-Z) Low (Drive) 70 440EP – PPC440EP Embedded Processor Min – 10 40% of nominal period 60% of nominal period 40% of nominal period 60% of nominal period T min T min IS IH ...
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... PPC440EP Embedded Processor Table 19. I/O Specifications—PCI, USB, UART, IIC, SPI, Ethernet, System and Debug Interfaces (Sheet Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. EMCSync is a weak driver. Redrive EMCSync when driving more than one load. ...
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... UARTn_Tx UARTn_DCD UARTn_DSR UARTn_CTS UARTn_DTR UARTn_RI UARTn_RTS USB1DevXcvr USB1DevXcvr USB1HostXcvr USB1HostXcvr USB2DI0:7 7 USB2DO0:7 USB2LS0:1 5.2 USB2OM0:1 USB2RxAct 7 USB2RxDV USB2RxErr USB2Susp USB2TermSel USB2TxRdy 6 USB2TxVal USB2XcvrSel Interrupts Interface IRQ0:9 72 440EP – PPC440EP Embedded Processor Output (ns) Valid Delay Hold Time min) (T max) (T min 3 3 ...
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... PPC440EP Embedded Processor Table 19. I/O Specifications—PCI, USB, UART, IIC, SPI, Ethernet, System and Debug Interfaces (Sheet Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. EMCSync is a weak driver. Redrive EMCSync when driving more than one load. ...
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... PerR/W 4 PerWBE0:1 4 External Master Peripheral Interface BusReq ExtAck ExtReq 4 ExtReset HoldAck HoldReq 4 HoldPri 4 PerClk PerErr 6 NAND Flash Interface NFALE NFCE0:3 NFCLE NFRdyBusy 4 NFREn NFWEn 74 440EP – PPC440EP Embedded Processor Output (ns) Valid Delay Hold Time min) (T max) (T min 0 7.2 1 ...
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... PPC440EP Embedded Processor DDR1 SDRAM I/O Specifications The DDR1 SDRAM controller times its operation with internal PLB clock signals and generates MemClkOut0 from the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut0 is the same frequency as the PLB clock signal and is in phase with the PLB clock signal ...
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... Signal Path Write Data MemData00:07 MemData08:15 MemData16:23 MemData24:31 ECC0:7 DM0:8 MemClkOut0 MemAddr00:12 BA0:1 RAS CAS WE BankSel0:3 ClkEn0:3 DQS0:8 76 440EP – PPC440EP Embedded Processor Output Current (mA) I/O H (maximum) 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 15.2 I/O L (minimum) 15 ...
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... PPC440EP Embedded Processor DDR SDRAM Write Operation The following diagram illustrates the relationship among the signals involved with a DDR write operation. Figure 9. DDR SDRAM Write Cycle Timing PLB Clk MemClkOut0 MemClkOut0(90) Addr/Cmd DQS MemData T = Delay from rising edge of MemClkOut0(0) to rising/falling edge of signal (skew) ...
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... SD HD 1/4 of the cycle time for the lower clock frequency (e.g., T Signal Names MemData00:07, DM0 MemData08:15, DM1 MemData16:23, DM2 MemData24:31, DM3 ECC0:7, DM8 78 440EP – PPC440EP Embedded Processor DS - 5.625 + 0.75T ). DS CYC Minimum 5.76 5.78 5.82 5.79 5 ...
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... In operation, following the receipt of an address and read command from the PPC440EP, the SDRAM generates data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440EP using a DQS signal that is delayed 1 cycle. In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency ...
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... In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually a slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal routing recommended that the signal length for all of the eight DQS signals be matched. 80 440EP – PPC440EP Embedded Processor Stage 3 Stage 2 D ...
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... Except for small, low frequency memory systems with the memory located physically close to the PPC440EP unlikely that Stage 1 data can be sampled. When the data comes later necessary to sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing ...
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... ECC Low High Data in at RDSP with ECC Low High Data out at RDSP without ECC Low T = Propagation delay from Stage 2 input to RDSP input w/o ECC Propagation delay from Stage 2 input to RDSP input with ECC TE 82 440EP – PPC440EP Embedded Processor ...
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... PPC440EP Embedded Processor Example 3: In this example, ECC is enabled. This requires that Stage 3 data be sampled at (3). If ECC is disabled, the system will still work, but there will be more latency before the data is sampled into RDSP. In this example, T system dependent and taken into account by controller initialization software. ...
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... During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the PPC440EP sequentially reads 16 bytes from the ROM device on the IIC0 port and sets the SDR0_SDSTP0, SDR0_SDSTP1, SDR0_SDSTP2 and SDR0_SDSTP3 registers accordingly. The initialization settings and their default values are covered in detail in the PowerPC 440EP User’ ...
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... PPC440EP Embedded Processor Revision Log Date Version 08/21/2003 09/22/2003 10/07/2003 10/13/2003 10/31/2003 11/03/2003 11/25/2003 12/15/2003 12/19/2003 01/12/2004 03/15/2004 04/7/2004 09/2/2004 09/8/2004 09/28/2004 10/06/2004 10/12/2004 10/28/2004 11/18/2004 11/19/2004 11/22/2004 12/17/2004 01/18/2005 01/31/2005 02/08/2005 AMCC Proprietary Contents of Modification Initial creation of document. ...
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... Added definition for RDSP abbreviation to DDR SDRAM Read Data Path figure. Added notes 3 and 4 to Recommended DC Operating Conditions table. Added Overshoot/Undershoot specification. Removed references to PPC440EP Rev B part number since these parts are no longer available for ordering. Replaced 16750 compatible UART to 16550 Replaced NS16750 with NS16550 ...
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... PPC440EP Embedded Processor 215 Moffett Park Drive, Sunnyvale, CA 94089 Phone: (408) 542-8600 — Fax: (408) 542-8601 AMCC reserves the right to make changes to its products, its data sheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available data sheet. Please consult AMCC’ ...