PPC405GPR-3KB266 Applied Micro Circuits Corporation, PPC405GPR-3KB266 Datasheet
PPC405GPR-3KB266
Specifications of PPC405GPR-3KB266
Available stocks
Related parts for PPC405GPR-3KB266
PPC405GPR-3KB266 Summary of contents
Page 1
... Four channels • PCI Revision 2.2 compliant interface (32-bit 66MHz) Description Designed specifically to address embedded applications, the PowerPC 405GPr (PPC405GPr) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-performance RISC ...
Page 2
... Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I/O Specifications—Group I/O Specifications—Group PPC405GPr Legacy Mode Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PPC405GPr New Mode Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2 Revision 2.05 – March 24, 2008 Data Sheet AMCC ...
Page 3
... Revision 2.05 – March 24, 2008 Data Sheet Figures PPC405GPr Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 27mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 35mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5V-Tolerant Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 AMCC 405GPr – Power PC 405GPr Embedded Processor ...
Page 4
... Ordering, PVR, and JTAG Information Product Name Order Part Number PPC405GPr PPC405GPr-3BB266 PPC405GPr PPC405GPr-3JB266 PPC405GPr PPC405GPr-3BB266Z PPC405GPr PPC405GPr-3JB266Z PPC405GPr PPC405GPr-3DB266 PPC405GPr PPC405GPr-3KB266 PPC405GPr PPC405GPr-3DB266Z PPC405GPr PPC405GPr-3KB266Z PPC405GPr PPC405GPr-3BB333 PPC405GPr PPC405GPr-3JB333 PPC405GPr PPC405GPr-3BB333Z PPC405GPr PPC405GPr-3JB333Z PPC405GPr PPC405GPr-3DB333 PPC405GPr PPC405GPr-3KB333 PPC405GPr PPC405GPr-3DB333Z PPC405GPr PPC405GPr-3KB333Z PPC405GPr ...
Page 5
... B: 35mm, 456 E-PBGA, -40°C to +85°C D: 27mm, 456 E-PBGA, -40°C to +85°C J: 35mm, 456 E-PBGA lead-free, -40°C to +85°C K: 27mm, 456 E-PBGA lead-free, -40°C to +85°C AMCC 405GPr – Power PC 405GPr Embedded Processor PPC405GPr-3BB266x Shipping Package Blank = Tray Z = Tape and reel Processor Speed 266MHz ...
Page 6
... Arb Code Decompression (CodePack™) SDRAM Controller 13-bit addr 32-bit data The PPC405GPr is designed using the IBM blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnect 6 OCM Power SRAM Mgmt DCRs ...
Page 7
... The PPC405GPr incorporates two simple and separate address maps. The first address map defines the possible use of address regions that the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC405GPr processor through the use of mtdcr and mfdcr instructions. ...
Page 8
Power PC 405GPr Embedded Processor DCR Address Map 4KB Device Configuration Registers Function 1 Total DCR Address Space By function: Reserved Memory Controller Registers External Bus Controller Registers Decompression Controller Registers Reserved On-Chip Memory Controller Registers Reserved PLB ...
Page 9
Revision 2.05 – March 24, 2008 Data Sheet On-Chip Memory (OCM) The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the processor core. Features include: • Low-latency access to critical instructions and data ...
Page 10
... Supports PowerPC processor boot from PCI memory SDRAM Memory Controller The PPC405GPr Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to four physical banks 256MB per bank are supported maximum of 1GB. Memory timings, address and bank sizes, and memory addressing modes are programmable ...
Page 11
Revision 2.05 – March 24, 2008 Data Sheet - Programmable CSon, CSoff relative to address - Programmable OEon, WEon, WEoff ( clock cycles) relative to CS • Programmable address mapping • Peripheral Device pacing with external “Ready” • ...
Page 12
Power PC 405GPr Embedded Processor Serial Interface • One 8-pin UART and one 4-pin UART interface provided • Selectable internal or external serial clock to allow a wide range of baud rates • Register compatibility with NS16550 register ...
Page 13
Revision 2.05 – March 24, 2008 Data Sheet Universal Interrupt Controller (UIC) The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the local PowerPC processor. Features include: • Supports 13 ...
Page 14
... SOLDERBALL x 456 14 Part Number 24 TYP A 27.0 25.0 1.0 TYP Thermal Balls PCB Substrate ∅ 0. ∅ 0. Revision 2.05 – March 24, 2008 Data Sheet Logo View ® PPC405GPr 1YWWBZZZZZ CCCCCCC Lot Number C 0. 0.25 0.35 C Mold Compound ± 0.5 0.1 2.65 max AMCC ...
Page 15
... SOLDERBALL x 456 AMCC 405GPr – Power PC 405GPr Embedded Processor Part Number 30.0 Typ A 35.0 31.75 1.27 PCB Substrate 2.65 max ∅ 0. ∅ 0. Logo View ® PPC405GPr 1YWWBZZZZZ CCCCCCC Lot Number C 0. 0.25 0.35 C Mold Compound ± 0.6 0.1 15 ...
Page 16
... Power PC 405GPr Embedded Processor Pin Lists The PPC405GPr embedded controller is available as a 456-ball E-PBGA leaded or lead-free package. The 456- ball package is available in two sizes—35 millimeters and 27 millimeters. In this section there are two tables that correlate the external signals to the physical package pin (ball) on which they appear. ...
Page 17
Revision 2.05 – March 24, 2008 Data Sheet Signals Listed Alphabetically Signal Name Ball EMCTxErr K25 EOT0/TC0 F3 EOT1/TC1 G2 EOT2/TC2 V2 EOT3/TC3 Y1 ExtAck Y3 ExtReq Y4 ExtReset A11 A16 A19 A21 A26 B2 B25 ...
Page 18
Power PC 405GPr Embedded Processor Signals Listed Alphabetically Signal Name Ball AB9 AB13 AB14 AB18 AB22 AC4 AC23 AD3 AD24 AE1 GND AE2 AE25 AF1 AF6 AF8 AF11 AF16 AF21 AF25 AF26 Gnt[PCIReq0] C19 GPIO1[TS1E] D18 GPIO2[TS2E] C20 ...
Page 19
Revision 2.05 – March 24, 2008 Data Sheet Signals Listed Alphabetically Signal Name Ball MemAddr0 AE22 MemAddr1 AC21 MemAddr2 AE21 MemAddr3 AD21 MemAddr4 AF22 MemAddr5 AE20 MemAddr6 AC19 MemAddr7 AE19 MemAddr8 AD19 MemAddr9 AC18 MemAddr10 AF19 MemAddr11 AD18 MemAddr12 AC17 ...
Page 20
Power PC 405GPr Embedded Processor Signals Listed Alphabetically Signal Name Ball B17 C13 E19 E20 E21 F5 F22 G5 G22 H5 H22 K2 N24 U25 W5 W22 Y5 Y22 AA5 AA22 AB6 ...
Page 21
Revision 2.05 – March 24, 2008 Data Sheet Signals Listed Alphabetically Signal Name Ball PCIClk B20 PCIDevSel H25 PCIFrame J24 PCIGnt0[Req] U23 PCIGnt1 T23 PCIGnt2 F23 PCIGnt3 H26 PCIGnt4 N23 PCIGnt5 M24 PCIIDSel P26 PCIINT[PerWE] C23 PCIIRDY J23 PCIParity E26 ...
Page 22
Power PC 405GPr Embedded Processor Signals Listed Alphabetically Signal Name Ball PerCS0 B3 PerCS1[GPIO10] C4 PerCS2[GPIO11] C5 PerCS3[GPIO12] A4 PerCS4[GPIO13] B9 PerCS5[GPIO14] B10 PerCS6[GPIO15] A9 PerCS7[GPIO16] B11 PerData0 U4 PerData1 U3 PerData2 U1 PerData3 T4 PerData4 R2 PerData5 ...
Page 23
Revision 2.05 – March 24, 2008 Data Sheet Signals Listed Alphabetically Signal Name Ball PHYRxErr U24 PHYTxClk E25 RAS AF24 C25 E23 E24 Reserved Y23 Y26 1 AF4 Req[PCIGnt0] U23 SysClk A25 SysErr AD25 SysReset D22 TCK AD22 TDI AE24 ...
Page 24
Power PC 405GPr Embedded Processor Signals Listed Alphabetically Signal Name Ball E10 E11 E12 E15 E16 E17 K5 K22 L5 L22 M5 M22 R22 T5 T22 U5 U22 AB10 AB11 AB12 AB15 AB16 AB17 WE ...
Page 25
Revision 2.05 – March 24, 2008 Data Sheet Signals Listed by Ball Assignment Ball Signal Name Ball A1 GND B14 A2 GND B15 A3 PerAddr1 B16 A4 PerCS3[GPIO12] B17 A5 PerAddr8 B18 A6 GND B19 A7 DMAReq3 B20 A8 PerAddr15 ...
Page 26
Power PC 405GPr Embedded Processor Signals Listed by Ball Assignment Ball Signal Name Ball J1 PerData23 M5 J2 PerData26 M11 J3 PerData25 M12 J4 PerData27 M13 J5 GND M14 J22 GND M15 J23 PCIIRDY M16 J24 PCIFrame M22 ...
Page 27
Revision 2.05 – March 24, 2008 Data Sheet Signals Listed by Ball Assignment Ball Signal Name Ball AA25 PHYCol AC8 AA26 GND AC9 AB1 MemData24 AC10 AB2 MemData21 AC11 AB3 GPIO9[TrcClk] AC12 AB4 UART0_CTS AC13 AB5 GND AC14 OV AB6 ...
Page 28
... PPC405GPr has control of the external bus. When, during the course of normal chip operation, an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC405GPr. In this example, the pins are also bidirectional, serving as both inputs and outputs. ...
Page 29
... When the PCI bridge is unused, configure the PCI controller to park on the bus and actively drive PCIAD31:0, PCIC3:0[BE3:0], and the remaining PCI control signals by doing the following: - Strap the PPC405GPr to disable the internal PCI arbiter and to operate the PCI interface in synchronous mode. ...
Page 30
Power PC 405GPr Embedded Processor Signal Functional Description Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down ...
Page 31
Revision 2.05 – March 24, 2008 Data Sheet Signal Functional Description Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and ...
Page 32
... Peripheral data bus used by PPC405GPr when not in external master mode, otherwise used by external master. PerData0:31 Note: PerData0 is the most significant bit (msb) on this bus. Peripheral address bus used by PPC405GPr when not in external master mode, otherwise used by external master. PerAddr0:31 Note: PerAddr0 is the most significant bit (msb) on this bus. ...
Page 33
... When the PPC405GPr is the bus master, it enables the selected device to drive the bus. Used by the PPC405GPr when not in external master mode, as output by either the peripheral controller or DMA controller depending upon the type of transfer involved. High indicates a read from PerR/W memory, low indicates a write to memory ...
Page 34
... HoldPri master tenure. Used when the PPC405GPr needs to regain control of peripheral BusReq interface from an external master. An input used to indicate to the PPC405GPr that an external slave PerErr peripheral error occurred. Internal Peripheral Interface Serial Clock used to provide an alternate clock to the internally generated serial clock. Used in cases where the allowable internally UARTSerClk generated baud rates are not satisfactory ...
Page 35
... JTAG test clock. The frequency of this input can range from DC to TCK 25MHz. JTAG reset. TRST must be low at power-on to initialize the JTAG TRST controller and for normal operation of the PPC405GPr. System Interface SysClk Main system clock input. Main system reset. External logic can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset ...
Page 36
Power PC 405GPr Embedded Processor Signal Functional Description Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down ...
Page 37
Revision 2.05 – March 24, 2008 Data Sheet Signal Functional Description Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and ...
Page 38
... I/O pins before OV is within operating range. DD Package Thermal Specifications The PPC405GPr is designed to operate within a case temperature range of -40°C to +85°C E-PBGA packages (leaded and lead-free convection environment are as follows: Package—Thermal Resistance 35mm, 456-balls—Junction-to-Case 35mm, 456-balls—Case-to-Ambient 27mm, 456-balls— ...
Page 39
Revision 2.05 – March 24, 2008 Data Sheet Recommended DC Operating Conditions Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Notes: 1. PCI drivers meet PCI specifications. 2. See ...
Page 40
Power PC 405GPr Embedded Processor 5V-Tolerant Input Current 50 0 -50 -100 -150 -200 -250 -300 -350 0.0 1.0 Input Capacitance Parameter 3.3V LVTTL I/O 5V tolerant LVTTL I/O PCI I/O Rx only pins 40 2.0 3.0 4.0 ...
Page 41
... In general, the values were measured using a PPC405GPr Evaluation Board with four PCI devices, an external bus master on peripheral bus, and external wrap-back on the Ethernet port. For all CPU clock rates, PLB = 133.3MHz, OPB = PerClk = 66.6MHz, PCI = SysClk = 33 ...
Page 42
Power PC 405GPr Embedded Processor Test Conditions Clock timing and switching characteristics are specified in accordance with operating conditions shown in the table “Recommended DC Operating Conditions.” For all signals other than PCI signals, AC specifications are characterized ...
Page 43
Revision 2.05 – March 24, 2008 Data Sheet Clocking Specifications Symbol Parameter CPU PF Processor clock frequency C PT Processor clock period C SysClk Input SCF Clock input frequency C SCT Clock period C SCT Clock edge stability (phase jitter, ...
Page 44
... Ethernet operation is unaffected. 4. IIC operation is unaffected. Caution the system designer to ensure that any SSCG used with the PPC405GPr meets the above requirements and does not adversely affect other aspects of the system. 44 Revision 2.05 – March 24, 2008 ...
Page 45
Revision 2.05 – March 24, 2008 Data Sheet Peripheral Interface Clock Timings Parameter PCIClk input frequency (asynchronous mode) PCIClk period (asynchronous mode) PCI Clock frequency (synchronous mode) PCI Clock period (synchronous mode - Note 2) PCIClk input high time PCIClk ...
Page 46
Power PC 405GPr Embedded Processor Input Setup and Hold Waveform Clock Inputs Output Delay and Float Timing Waveform Clock T max OV T min Outputs OH High (Drive) Float (High-Z) Low (Drive min T min IS ...
Page 47
Revision 2.05 – March 24, 2008 Data Sheet Notes all of the following I/O Specifications tables a timing values of “na” means “not applicable” and “dc” means “don’t care.” 2. See “Test Conditions” on page 42 for output ...
Page 48
Power PC 405GPr Embedded Processor I/O Specifications—Group 1 Notes: 1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. In synchronous mode, timing is relative to ...
Page 49
Revision 2.05 – March 24, 2008 Data Sheet I/O Specifications—Group 1 Notes: 1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. In synchronous mode, timing is relative ...
Page 50
... SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405GPr package pin. System designers must use the PPC405GPr IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring ...
Page 51
... The PPC405GPr can be used as a replacement for the PPC405GP. When the PPC405GPr is used for this purpose, it should be strapped to operate in the PPC405GPr Legacy Mode. This option is selected by strapping ball D20 (GPIO24) low (0). If Legacy Mode is selected, the “PPC405GPr Legacy Mode Strapping Pin Assignments” ...
Page 52
... The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the PPC405GPr. These bits are shown for information only; and do not require modification except in special clocking circumstances such as spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GPr, visit the technical documents area of the AMCC PowerPC web site. 2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “ ...
Page 53
... Revision 2.05 – March 24, 2008 Data Sheet PPC405GPr New Mode Strapping Pin Assignments Function PLL Tuning See the PowerPC 405GPr Embedded Processor User’s Choice 1; TUNE[9:0] = 1010111100 Manual for details. Choice 2; TUNE[9:0] = 0100111000 Choice 3; TUNE[9:0] = 0100110110 Choice 4; TUNE[9:0] = 0100111100 Choice 5; TUNE[9:0] = 0100111000 Choice 6 ...
Page 54
... Power PC 405GPr Embedded Processor PPC405GPr New Mode Strapping Pin Assignments Function 2, 3 PLL Feedback Divider 2 OPB Divider from PLB 2, 3 PCI Divider from PLB External Bus Divider from 2 PLB ROM Width ROM Location PPC405GPr Peripheral Attach PPC405GPr PCI Attach ...
Page 55
... The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the PPC405GPr. These bits are shown for information only; and do not require modification except in special clocking circumstances such as spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GPr, visit the technical documents area of the AMCC PowerPC web site. 2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “ ...
Page 56
Power PC 405GPr Embedded Processor Printed in the United States of America, Monday, March 24, 2008 The following are trademarks of AMCC in the United States, or other countries, or both: AMCC Other company, product, and service names ...
Page 57
... AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2008 Applied Micro Circuits Corporation. AMCC 405GPr – Power PC 405GPr Embedded Processor Applied Micro Circuits Corporation http://www ...